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To: wanna_bmw who wrote (73761)	3/6/2002 6:13:47 PM
From: Ali Chen	Respond to of 275872

"Yes. That was a fact. You were incorrect in your assumption, but that's ok. Everyone is wrong from time to time." There is also a fact that technically-challenged PR stooges call Rambus a 800-MHz memory. It does not change the internal structure of 100-MHz DRAM blocks inside DRDRAM chips. I repeat last time: The best research-grade samples of early 0.13um silcon (dubbed "70nm Leff") yielded 1.6HGz at most. The recent 0.13/60-enhanced process yielded Pentium-4 at 2.5GHz. Reduction of Leff by 15% cannot result in 56% speedup in SRAM frequency. Period. Therefore it is physically impossible to make a "full-speed" 2.2HGz cache without two-bank interleaved design. That's why there are two identically-looking cache blocks on die photos. Formally, at the interface point, it behaves as a full-speed cache, true, that's where all your (and your PR stooges) confusions came from. - Ali