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To: milo_morai who wrote (74112)3/9/2002 3:44:59 AM
From: Ali ChenRead Replies (2) | Respond to of 275872
 
Milo, "..the effect is likely even more pronounced than you infer".

The guy constructed his example using three assumptions,
about cacheline fill time, about cache miss rate, and
about cache latency. He got the "total latency
domination" and 10% gain per 50% speedup solely by this
arbitrary construction. His assumption could be valid
for some single task, but it is not what the industry
benchmarks are today. According to me, in SPEC2000int,
the P4 gains 32% per 50% speedup in clock frequency,
from 2000 to 3000MHz, and for SPEC2000fp the gain
is 20% for the same speedup. The "througput" calculations
have limited use, same as IPC: who cares if IPC
is slightly higher, but the clock is way below competition.

- Ali