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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (162377)	3/16/2002 5:06:35 PM
From: Dan3	Respond to of 186894

Re: My previous post. I re-read it, and noticed that due to moving a paragraph around, one part is a little confusing: One of the ways P4 makes up for this with an aggressive prefetch strategy - as the program runs, a sort of shotgun approach sends memory read requests for a number of locations in memory that might or might not soon be needed by the chip. But, since P4 is reading a number of locations that will not be used, it ties up memory bandwidth, never using many of the prefetch reads it performs. Athlon also does some prefetch, but less than P4. This refers to making up for the fast, but "shallow" P4 cache's limited caching ability. Aggressive pre-fetching exacerbates the demands P4's cache makes on the memory subsystem, it doesn't make up for it. I also misspelled Prefetch in one place - please accept my apologies for that error, and try to get past it to the remainder of the post.