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To: wanna_bmw who wrote (162395)3/17/2002 6:55:42 PM
From: wanna_bmw  Read Replies (1) | Respond to of 186894
 
Presentation on future Flash Technologies

intel.com

Sorry if this has been posted already. It describes several new flash technologies that Intel is pursuing, and also gives some good information on current technologies.

wbmw



To: wanna_bmw who wrote (162395)3/17/2002 8:05:13 PM
From: Elmer  Read Replies (4) | Respond to of 186894
 
Thanks Wanna. A couple of comments:

How does this SRAM demonstrate 7 layers of Cu? That's what the paper claims.

The comment "World's smallest SRAM call, at 1Um2 illustrates Intel's ability to build very large caches and very high density for maximum performance"

Clearly very large caches and very high bandwidth are key to Intel's vision of the future. Compare this to the competition who has never manufactured any large cache devices. Their only attempt, Mustank, ended in failure, probably due to yield problems.

The only other company to claim functional 90nm devices is TSMC. Their SRAM cell is 30% larger, they have only 4MB working units and they will have 65nm gates at their 90nm node. Intel is almost there already on their .13u process and will be <50nm at 90nm node.

e-insite.net

It's exciting to see Intel hitting on all cylinders while the competition is belching smoke and leaking oil.

EP



To: wanna_bmw who wrote (162395)3/17/2002 9:37:36 PM
From: Paul Engel  Respond to of 186894
 
Beamer - Re: "This test chip was manufactured at Intel's 300
mm development fab, D1C, in Hillsboro, Oregon
• The process will be transferred to other 300 mm
manufacturing fabs"

Gee...how many other companies can transfer a 0.09 Micron 7 layer Copper process from one 300 mm Wafer Fab to their other 300 mm wafer manufacturing fabs?

Rather a unique position Intel is in, eh?

Paul