SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (162414)3/17/2002 10:27:35 PM
From: Dan3  Read Replies (1) | Respond to of 186894
 
Re: If the die size can be reduced by at LEAST 12%, it is a wash.

If the same circuitry can be fit on a smaller die, particularly if you're achieving that by using more direct (shorter) routing, then the chip can clock higher. At 4GHZ, about 1/3 of a clock is used up moving from one side of a 100mm2 (10 x 10) die, to the other side. If the trace is routed around other traces, 1/2 the clock (or more) can be used up just moving across the die. If you're only moving halfway across the die, it still amounts to 1/4 of the clock. Cut down the die size, and you can allow more time for the transistors to switch at a given mhz. In other words, the same transistors, in the same basic design, aided by shorter traces from extra layers, can result in a chip that can clock higher.

So, as you said, if the shrink is as great in percent as the increase in fabrication time, there is little cost increase. But even if the costs are a little higher, the smaller die should be able to clock somewhat higher - say it's 10% - what is that worth?