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To: wanna_bmw who wrote (162425)3/18/2002 6:39:28 AM
From: TGPTNDR  Read Replies (1) | Respond to of 186894
 
Wanna, Re: <Needless to say, I couldn't find any indication of how many layers AMD plans on using.>

He[Jerry] said "9 layers of metal". He said "Silicon on insulator". He said 100M transistors. He said model 3400+ by year end.

Message 17157180

tgptndr



To: wanna_bmw who wrote (162425)3/18/2002 7:10:17 AM
From: Joseph Pareti  Read Replies (1) | Respond to of 186894
 
just visited the Intel stand at cebit. Some highlights

"make computer TALK"

- Intel "other" is big (my impression), 10 GB Ethernet, xscale all over the place: iop, cell phones, network processors, ...

- embedded space, appliances, reference platforms

- dozens of P4 motherboards.

- a cool reference set-up for (car) crash simulations at audi, viz on a foster workstation, sys integration with lsf, number crunching on a bunch of xeon boxes running linux, pamcrash, nastran, ...

- enterprise servers, a big chunk of the floor space
(almost bigger than sun :-)

- mysap, oracle 9irac on Itanium.

- game area on 2.2 GHZ p4



To: wanna_bmw who wrote (162425)3/18/2002 9:11:40 AM
From: combjelly  Read Replies (1) | Respond to of 186894
 
" I thought I remember several people here claiming that AMD's .13u process had 9 metal layers"

AMD's 0.13 micron process allows for up to 9 metal layers, Intel's allows for 6.
chip-architect.com