Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fyodor_ who wrote (74947)	3/19/2002 12:00:21 PM
From: combjelly	Read Replies (2) \| Respond to of 275872

"Model rating = 1300 + (f - 1200)*100/66" Apparently that changes at 2200+... planet3dnow.de

To: fyodor_ who wrote (74947)	3/19/2002 1:13:34 PM
From: Ali Chen	Read Replies (1) \| Respond to of 275872

Fyo, "This contradicts your claim that "the difference between consecutive scores should not drop faster than it started at"." Do not play pgerassi. I did not start at 0 frequency. I started from 1500-1600-1700-1800 point where the d²P/df² appears to be flat. And my argument was that the 3x-jump in second derivative can't happen unless BIOS made compulsory configuration changes to something. "However, in the AthlonXP vs P4 case, there is a huge difference in available bandwidth. This significantly impacts not only performance, but also scaling. Same goes for larger caches, although this is certainly harder to compare directly, since the caches are very different in nature (latency, bandwidth and associativity - along with size)." It all is true and relevant, but it does not lead us to any conclusion. The bottom line is the value of memory wall for each particular platform, see definitions complang.tuwien.ac.at ftp://ftp.cs.virginia.edu/pub/techreports/CS-94-48.ps.Z For example, FSB can be slow but cache may be more effective, and faster FSB/memory may be coupled with less effective cache. In both cases the memory wall might be the same, then a CPU with higher internal IPC will win, again depending on the top frequency of the design. So, go figure. - Ali

To: fyodor_ who wrote (74947)	3/19/2002 3:38:58 PM
From: AK2004	Respond to of 275872

fyodor I think I already mentioned that amd said that they would use a simplified conservative formula over some limited range of frequencies and adjust the formula when needed. you made a good argument about that if the ratio of slopes would remain the same then we would see relative performance degradation of athlon. 1) we really need to use some simple model to incorporate uncertainty for relative performance increase, something like d(r) = k( target - r ) dt + sigma dz 2) QS really is a bad measure because there is no fixed formula for calculating it so more appropriate would be to compare dP/dt that is growth of performance with time the problem with 2) is that both of the companies are coming with new processors very hard if not impossible. good example would be intro of athlon that had good scaling vs intel's pIII topping out. Applying dP/df or dP/dt logic without consideration for possible changes would lead to end of intel. In fact, no one thought that that would happened and in a short while came faster p4. Regards -Albert