Yousef - Remember when Rotomola traded MAD Copper Rear End for embedded flash technology?
Here's another confirmation that Rotomola got shafted by MAD and had to cut a separate deal with SST for embedded flash technology.
"Split-gate approach
That is possible because the flash is much faster to program. The HCS12 family is based on a split-gate flash technology licensed from Silicon Storage Technology Inc. (Sunnyvale, Calif.), with flash densities ranging from 64 kbytes up to 512 kbytes. "
Six-Figure-Hector's legacy lives on !!
Paul
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Motorola spices up flash for 16-bit MCU line
By David Lammers, EE Times
Mar 18, 2002 (9:15 AM)
URL: eetimes.com
AUSTIN, Texas — Motorola Inc.'s Semiconductor Products Sector will introduce a new line of 16-bit microcontrollers Monday (March 18) with flash modules that are larger and much faster to program than current implementations.
Paul Grimme, general manager of Motorola's 8- and 16-bit Microcontroller Division, said the company's dominance in the 8-bit arena has not been duplicated in the general-purpose 16-bit MCU market. "We rank third among 16-bit controller vendors," behind Hitachi Ltd. and Mitsubishi Electric Corp., he said. "One reason is that we've put our attention on automotive. What we plan to do is take our success in 16-bit automotive MCUs and translate that into the wider 16-bit MCU market," Grimme said.
The new HCS12 line also is positioned as an upgrade path for many users of Motorola's nearly ubiquitous HC11 8-bit flash controllers, which have an earlier-generation flash technology, Grimme said. About a billion units of the HC11 family have shipped over the past decade.
The HCS12 line runs at 25 MHz, has a more complex set of peripherals and supports real-time debugging through a single pin. The pin dedicated to debugging during development can be used later, on the production line, to program the flash module.
Split-gate approach
That is possible because the flash is much faster to program. The HCS12 family is based on a split-gate flash technology licensed from Silicon Storage Technology Inc. (Sunnyvale, Calif.), with flash densities ranging from 64 kbytes up to 512 kbytes.
The third-generation flash on the HCS12 family is an order of magnitude faster, Grimme said, partly because the second-generation split-gate flash was based on 0.5-micron process technology, while the HCS12 is made in a 0.25-micron process.
Motorola will first ship the HCS12 versions with 256 kbytes of flash, and will expand the line over the rest of this year to range from 64 kbytes up to 512 kbytes of flash.
James Sibigtroth, principal member of the technical board at the Microcontroller Division, said programming that flash is now much easier. "In the past, the user had to write his code to insert a delay after turning on his high-voltage supply, and another delay after selecting a certain byte, and then time the programming operation. It was a medium-complexity programming routine to program a location," he said. "With the HCS12, to write a value to the flash, the programmer writes a command to do a programming operation, and waits for the flag that says it's done."
In the field, Sibigtroth estimated that a 256-kbyte flash module can be programmed in about 5 seconds, with most of that time swallowed up by the time it takes to get the data to the control logic.
"A random byte takes 45 milliseconds, or in burst mode about 20 microseconds per 16-bit word. The older parts used a kind of EEPROM technology that was 10 to 100 times longer. That will allow most users to program the parts right on the factory floor, on production boards. The reliability of the end product goes way up if you never touch the package," Sibigtroth said.
The HCS12 also has a much-improved indexed addressing function, Sibigtroth said, one reason users of the 8-bit HC11 may want to consider upgrading to the 16-bit HCS12. The indexed addressing mode on the HC11 supports an 8-bit positive-only offset from an indexed register value, with two registers, X and Y, to choose from. And he said there is a time and code expense if the second register is used.
In addition to the two registers in the index register, engineers can also work off the stack program counter, which is important for high-level language support. "The way we designed it, there is no penalty for using the stack program counter instead of the index register," Sibigtroth said.
Sharp point
The architecture also supports accumulating offsets, which "are useful if you think about the 8-bit constant offset only, when you have to know where to point when you write the program," Sibigtroth said.
Accumulating offsets allow the program to adjust the value in the accumulator as the program is executing. The value in the accumulator can then be added to the index register to point to the location where the programmer wants to look.
Sibigtroth said automatic pre- and post- increment-decrement also are supported. In the HC11, the amount of increment-decrement was tied to the size of the operand being manipulated. With the HCS12, the amount of increment and decrement can be independent, and can be as large as eight. The amount can vary from one to eight, either positive or negative. When programmers work with small data structures, the instructions to update the index registers can be incorporated into one of the operations in the program. "That is a significant way to get higher code efficiency on a high-level language," Sibigtroth said.
Sibigtroth helped define the instruction set on the HC11 back in 1980, and also contributed in recent years to the HCS12 architecture. He said the size of the bus determines a 16-bit architecture: everything is fetched from memory 16 bits at a time. "With the HCS12, we still have mostly 8-bit op codes, but we are fetching everything out of memory, 16 bits at a time," he said. "A no-op, which is a nothing that should take as few bits as possible, normally would take 16 bits of code space. Bit in the HCS12 we can use one, two or three bytes for an instruction, which makes more efficient use of memory and helps keep the C code more compact." |
