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To: dale_laroy who wrote (162688)	3/21/2002 1:59:15 PM
From: Tony Viola	Read Replies (2) \| Respond to of 186894

With Clawhammer having 512KB of 16-way set associative L2 cache versus Prescott having 1MB of 8-way set associative L2 cache, it should be a pretty good matchup with regards to cache hit rate. Dale, doubling the set associativity makes up for having half the L2 memory size with regard to cache hit rate? If so, why doesn't everyone go that way and save all that memory space? The logic for 16 way associativity (over 8 way) can't be anywhere near the size of another 512 KB of L2. Tony

To: dale_laroy who wrote (162688)	3/21/2002 4:02:58 PM
From: combjelly	Respond to of 186894

"This would also seem to confirm that Clawhammer will have 512KB L2 cache." Yep, it would. So they are packing about 30 million additional transistors into 24mm^2, much of that would have to be regular structures like cache. And this information gives us some interesting clues. According to sandpile.org, a Morgan has 25.2 million transistors. A Palomino has 37.5 million. That means the 192k of extra L2 cache is 12.3 million transistors, and that would imply that 256k would be 16.4 million. And that would mean that the extra HTT ports and wider memory bus on the SledgeHammer are only a few hundred thousand transistors, or they are already on the ClawHammer chip... Or, turn it around. A ClawHammer with a 256k L2 cache would be around 50 million transistors, or 50% larger than a Palomino with the same amount of cache. If we strip away all of the L2 cache, we see that the Palomino has about 20 million transistors, which is close to the K7 Classic with 22 million, and the ClawHammer has 34 million. So the ClawHammer core has about 70% more transistors than a Palomino core. And that means it has got to have the same number of HTT ports or there are a lot more changes than have been discussed so far. Or both.