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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: pgerassi who wrote (75570)3/25/2002 11:34:56 PM
From: YousefRead Replies (1) | Respond to of 275872
 
Pete,

Re: "Defect density does not vary that much between cutting edge fabs at similar
times as the wafers supplied to each fab come from the same sources ... And
most of those defects are caused by the underlying wafer are they not?"

You really are "clueless", Pete ... NO, most defects DO NOT come
from the "underlying" wafer. AND, "cutting edge" Fabs DO NOT have
the same defect density. A good example of this is LowK dielectric.
This process has a whole different type of defect relative to the
more standard FSG dielectric. The LowK dielectric process has a much
higher defect density than FSG. This is a FACT.

Re: "You forgot the most valuable point! The smaller die at the same defect
density has a much higher yield. In other words, big is bad!"

This is true ONLY if the smaller die provides the same performance and capability
of the larger die. I will let other so called "architeture experts" rant
and rave on this issue. <ggg> As a side note -> INTC does command
a higher ASP for their die ... May be due to higher performance and
capability ??!!

Make It So,
Yousef



To: pgerassi who wrote (75570)3/25/2002 11:40:11 PM
From: YousefRead Replies (1) | Respond to of 275872
 
Pete,

Re: "You forgot the most valuable point! The smaller die at the same defect
density has a much higher yield. In other words, big is bad!"

This is especially true at high defect densities (> .5d/cm^2).
I wonder if this is the reason that AMD is so hesitant to add larger
cache to their CPU's and make a bigger die size. Could this be
what "killed" them in previous process/designs ??!!

Make It So,
Yousef