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To: Ali Chen who wrote (162948)	3/26/2002 2:21:35 AM
From: wanna_bmw	Respond to of 186894

Ali, Re: "I am well aware of the prime purpose of that slide, but IMO it also slips an additional quantitative information, that there are parts capable of running at fairly higher frequencies, but they suffer significantly from excessive leakage, which obviously drives the parts out of thermal envelope, and consequently from the market, so far." So is that your theory for why Intel has yet to launch chips that run faster than 2.2GHz? What about mention of 3.0GHz chips by the end of the year? Will these be water cooled, or do you believe subsequent steppings would be capable of reducing the levels of leakage that you think are apparent at higher frequencies? wbmw

To: Ali Chen who wrote (162948)	3/26/2002 4:17:00 AM
From: THE WATSONYOUTH	Respond to of 186894

So, it still does not explain the published specifications of 17A. I remember suggesting that the 17A is the worst-case for mass-produced units, while the published device characteristics are for cherry-picked best samples. Is this totally out of line? Are there other not-yet-discoverd (published?) sources for such excessive standby current? Please note that they call this problem as "leakage", and it's severity was publicly acknowledged by Intel on several levels. Of course I am well aware of the prime purpose of that slide, but IMO it also slips an additional quantitative information, that there are parts capable of running at fairly higher frequencies, but they suffer significantly from excessive leakage, which obviously drives the parts out of thermal envelope, and consequently from the market, so far. I see your point and you are certainly not out of line. The 17A probably is an estimated worse case meaning minimum mean channel length (still meeting across chip line width variation requirements) with lowest possible Vt on all devices. The point is there are a few unknowns. Intel says L nominal = 60nm. They define L min = L nominal - CD control. But, what is the CD control?? Is it +/-80A 2 sigma? +/- 100A 3 sigma? What?? Also, what is the percentage of low Vt devices in the design? 2%? 4%? 10%? 40%? More? They claim the nominal low Vt device will have a Ioff of 100nA/um or 10x more than the standard Vt device. But if the CD control is say +/-80A 2 sigma from the minimum mean or L nominal of 60nm, then there are a few percent devices with channel lengths below 52nm. What are the off currents there? 20x higher yet? 50x higher? 100x higher? I'll try to work out a scenario (percent of low Vt devices combined with reasonable estimates of CD control and the associated off currents of the below nominal devices which could in total approach 17A. Of course you know none of this is of any concern until one approaches the minimum mean = L nominal = 60nm physical poly. As I said, I think the 2.2 GHz part is in the area of 80nm physical poly. You never really know how good your process control is until you work down at the minimum mean. There....everything matters ....big time. We'll see THE WATSONYOUTH

To: Ali Chen who wrote (162948)	3/26/2002 8:00:35 AM
From: Dan3	Respond to of 186894

Re: Please note that they call this problem as "leakage", and it's severity was publicly acknowledged by Intel on several levels. And was previously acknowledged by IBM, Motorola, and AMD and given as the main reason for moving to SOI on .13 - something every leading Semi FAB is doing, with the glaring exception of Intel, which is very late to SOI. Intel didn't move to Copper until .13, and wasn't able to keep up on .18. Now they expect to be without SOI on .13 and .09 (at least, their initial .09). Intel was only a little behind on .18, but on .13, and particularly on .09, the leakage issue could put a lot of pressure on them.

To: Ali Chen who wrote (162948)	3/28/2002 12:13:38 AM
From: THE WATSONYOUTH	Read Replies (2) \| Respond to of 186894

So, it still does not explain the published specifications of 17A. Please point me to the specification. I believe it must be a worse case spec. I would guess Intel measured some standby currents on functional chips down at what they call L nominal = Lmin + CD control = 60 nm. Now, remember... I think this L nominal actually is the minimum mean poly at which Intel expects to be able to ship a part assuming it meets some across chip linewidth variation of say +/- 80A 3 sigma. Intel claims such a 60nm device will have an off current or 100na/um for the low Vt case. The high Vt devices have off currents 10x lower and so do not contribute much especially if the low Vt devices comprise a significant percentage of the total devices on the chip. I'm now guessing that Intel uses low Vt for perhaps everything that runs at advertized freq. So that may well be 50% of the total devices. If you assume 25 million low Vt devices (mostly logic) and an average logic device width of 4um, you could get 10A standby current if you assume they all are at this 100na/um level. But, herein lies the problem and it is a big one. At 100na/um off current, the NFET still has a threshold of around 130mv. It's Ion/Ioff ratio still is around 10,000. If all the devices were like that, there would be no problem. However, these 25 million low Vt devices with a mean at 60nm actually have some distribution around that mean which is whatever Intel is getting for their across chip linewidth variation. This is a function of mask quality, lith quality, RIE quality, among other things. Despite what they may claim, I sincerely doubt it is better than +/- 80A 3 sigma around that mean of 60nm. And it is not necessarily the off current from the few devices down below the spec that is the problem. Even at 10,000nA/um, the Ion/Ioff ratio is 100:1. The problem is the threshold voltage of those few devices. I refer you again to Intel's chart from their 2001 IEDM paper of Vt vs L poly for the low Vt NFET at high drain bias. At 60nm, it is around 130mv. At 50nm, it is around 40mv. So, we have millions of devices in critical paths with Vts varying from above 130mv down to at least 50mv. Extremely dangerous, I would think. I can't believe this stuff will ever get shipped. As, I said previously, none of this is an issue until you get down to near that minimum mean of 60nm. From that paper, I don't see Intel reaching 3GHz with the process as it is now. The schmoo plot even shows it. And I doubt they would be so foolish to ship parts with 17A standby current even if they passed all stress tests. A stand by current that high guarantees that a significant number of devices are on that very steep roll off part of the Vt vs. L poly curve. It is extremely dangerous to operate there. I believe they will have to shrink the process further (perhaps 10-15% area)) and perhaps raise the voltage slightly to get a significant number of 3GHz parts. The IEDM paper specifically mentions a 5% linear shrink and I wouldn't doubt Intel would raise the voltage again to 1.55v or 1.6v if pressed and if additional stress readouts look promising. Makes sense??? THE WATSONYOUTH P.S. I remember a time when standby currents were of the order of several hundred milliamps.