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To: Yousef who wrote (75731)3/27/2002 12:58:30 PM
From: pgerassiRespond to of 275872
 
Dear Yousef:

Wrong again! Where is the information stored? On the memory dies. The CPUs have the first three levels of caches, L0 which is the registers on the CPU, L1 which is usually divided into data and instructions to be optimal for each type of access and L2 which is combined. As main memory size goes up, the effectiveness of these caches shrink as a single set covers more memory decreasing the hit rate.

Even your buddy Intel uses different sizes of cache to work with different amounts of memory. They use 128KB for small value systems, 256KB for desktops, 512KB for workstations and 1MB for servers. Yet, they could just use one size and vary the amount of L3 with the amount of memory installed. Smaller systems have 128MB of memory and use an L3 of 1MB to huge systems with 16GB and have a 128MB L3 all with the same CPU die. Less aggravation predicting which sizes need to be produced and when they guess wrong, the associated allocation problems. And they seem to guess wrong frequently.

Pete



To: Yousef who wrote (75731)3/27/2002 8:54:24 PM
From: Dan3Read Replies (1) | Respond to of 275872
 
Re: cache can't be located far from CPU (light travels roughly one foot per nanosecond).

I suppose that the speed of light in a vacuum makes sense for P4 (the thing's basically useless, anyway) but the fact that signals travel at about half that speed in metal might be worth considering...