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To: Yousef who wrote (75771)3/28/2002 11:11:57 AM
From: pgerassiRead Replies (1) | Respond to of 275872
 
Dear Yousef:

You are wrong! I did not say to get rid of current caches on the chips. I am saying that we are getting diminishing returns from on die cache as it is built now. It is latency that causes most of the trouble. Since main memory doesn't seem to get below 30ns (54ns for registered) or so, adding cache there to reduce it to 15ns will increase performance more than doubling L2 cache. Making CAS 1 DDRDRAM would reduce latency to 18ns at PC2700. It should be possible with some more intelligence on the die to get CAS 0.5 to reduce latency to 12ns. To do something similar with cache would require a 256KB cache to increase to about 5MB or making even a NW be about 460mm2. And that size is for on die memory controllers. Off die, the cache increase does not need to be as large to about 2MB or about 270mm2, but it will perform slower than an on die like Hammer with memory cache.

Is it worth doubling the die size wrt NW, 5/2s it wrt to Hammer or more than triple it wrt to Tbred? IMHO, it is not.

Pete