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To: Charles Gryba who wrote (76600)	4/6/2002 8:08:01 PM
From: Elmer	Read Replies (4) \| Respond to of 275872

Elmer, by hand picking I meant that they go to some extra step to determine which cpus can run reliably at these speeds. Anyway, as a side question, how do you think the P3 1.13 managed to sneak through this binning process and how can the prevent it from happening again? Typically manufacturing defects fall into one of two main categories, stuck at, and delay faults. A stuck at fault appears as though an internal node is stuck at either a 1 or 0 and can't be switched. A delay fault is not stuck at either state but instead has a greater than expected delay from one stage to the next. The method of modeling and optimizing a test program for testing stuck at faults is pretty well determined and measurable. Delay faults are not. There is no generally accepted method for determining an acceptable level of testing or how that is measured so for delay faults the general approach is to throw as much as reasonable/possible at it and hope for the best. It is impossible to cover all possible internal delay paths and even predicting them by simulation is not an exact science. Actually I should say that predicting them is easy it's just that the silicon doesn't really match predictions as well as one would like. Speed path analysis on real silicon is a very complicated process involving very expensive and sensitive equipment and Intel simply didn't cover enough of them (speed paths)in their test suite for the P3. System validation is also another tool used for verification and they must have missed that particular speed path in their SV lab as well. When you are struggling to get something out you are vulnerable to mistakes and that's what happened. EP