To: John F. Dowd who wrote (164479 ) 4/23/2002 8:09:05 PM From: Dan3 Read Replies (1) | Respond to of 186894 Re: Payback This isn't payback for anything. Merced / Itanium is neither necessary nor sufficient as a solution.Itanic: It's all academic now - Official By Andrew Orlowski in San Francisco Posted: 23/04/2002 at 07:37 GMT The name Itanic, coined here several years ago by Mike Magee, for Intel's IA-64 processor has been formally adopted by academia. Nick Weaver, a 28-year old graduate student and researcher, teaches computer science classes at the University of California's Berkeley school, and as you can see from his "special topics" class, week 16 next month will be devoted to the "Voyage of the Itanic". "Itanic describes the architecture very well," he tells us, explaining that the processor contains great ideas and "beautiful features" that ultimately were compromised by terrible subsequent design choices and "feature creep". We invited him to elaborate: "The first good idea was one they explored several years ago in a paper from HP. That explains that if you have 64 or 28 registers with 64 or 128 condition registers and every instruction is being conditionally executed, then to get to a statically-scheduled superscalar - you'd get benefits of VLIW- issue logic, which is very simple, without the upgrade problem that VLIW has." What upgrade problem? "VLIW doesn't scale because the compiler statically issues for the number of function units in the VLIW architecture . So for a new version of VLIW you have to recompile. Transmeta gets around this by always recompiling, and it's not a problem in the DSP community. But it is a problem if you want to do a 'general purpose' processor" Nick commends deferred exception handling and low-cost checkpointing as two "beautiful features" of the IA-64 architecture. "This also interacts well with the speculative techniques derived from the first part: You can speculatively execute both sides of a branch, allow cache misses to be errors which are deferred, and you only take the penalty if there is both a cache miss which is on the branch who's result you want. They make this very nice by propagating error conditions. read the rest (if you dare) at:theregister.co.uk