Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fyodor_ who wrote (78409)	4/25/2002 8:38:23 PM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

Fyo, IMHO, AMD is making a huge mistake in limiting the bandwidth of Clawhammer. Agreed. I think the whole ClawHammer should be scrapped, and only introduced later as a budget chip. SledgeHammer should be the only part sold in the Hammer line. Joe

To: fyodor_ who wrote (78409)	4/25/2002 9:06:15 PM
From: ptanner	Read Replies (1) \| Respond to of 275872

fyo, re: "AMD is making a huge mistake in limiting the bandwidth of Clawhammer." I guess I am not as concerned/aware about memory bottlenecks for the uses that interest me, particularly for a new architecture which has yet to provide test results. Enthusiasts who want/need the higher bandwidth can spring for Sledges and those without the bandwidth need can select Claw 2P. It would certainly be simpler and more cost-effective for all of the processors to have dual memory controllers from the point of view of providing for greater volume of motherboards. I am still curious about whether there will be two different sockets or just one with unused pins (and parallel memory banks) for Claw. Given the similar base designs of the Claw/Sledge how hard would it be for AMD to add dual memory for Clawhammer or to provide "small" cache Sledge Lite limited to 2P operation? AMD must know the answers on the cost/performance and should have made an informed design decision. -PT