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To: Joe NYC who wrote (78416)4/26/2002 1:03:03 AM
From: wanna_bmwRespond to of 275872
 
Joe, Re: "Memory cacheability up to 4 GB of addressable memory space and system memory scalability up to 64 GB of physical memory"

Actually, this is all dependent on the chipset. But as you know, the x86 architecture has several limitations. One of them, which is hilighted here, is the 4GB of addressable memory space, having been defined by the original 32-bit architecture extension. With registers that are only 32-bit in size, you can only manage memory in 4GB chunks. Xeon servers will go beyond 4GB, given the 36-bits of physical address lines, but all memory above 4GB must be accessed using the segment registers. Also, as I indicated before, MMIO space, interrupts, system memory ranges, etc, will all need logical memory space, thus reducing the amount of physical memory available to the system. How much is required, and how it is set up by the system, all depends on the BIOS and OS, which may differ from platform to platform.

The moral, though, is that IA-64 family processors have no such limitations. They can easily go beyond 4GB of memory without any special logic or programming. It's all a large, flat address space, so you will more likely find IA-64 platforms supporting larger memory arrays. Current Xeon platforms that I am aware of do not support more than 16GB of memory, but Itanium 2 platforms certainly will.

wbmw