Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (78626)	4/28/2002 2:50:42 PM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Ali: The fact is that interconnect delays only affect those chips that maintain the same die size as the process generations come and go. A 100mm2 die in 0.065u (65nm) has 4 times the transistors that a 100mm2 die in 0.13u (130nm). It supposedly should run twice as fast. However if you use only the number of transistors on 65nm as on 130nm, interconnect delays are the same relative to clock speed. Essentially they are saying that interconnect delays for 100mm2 dies become a greater factor versus logic speed as the processes shrink. I think that the actual designs will not stay constant. The core size will shrink as the process shrinks just not as much. The L1 caches will stay roughly the same in die area compared to the core. L2 will grow relative to the core and stay about the same in die area. Higher level caches and logic may add to that, but what I think will happen is that more core functions will clump and the die will contain more cores in addition to the GP CPU core. Like GPUs, DRAM controllers, DSPs, Data Links and Switches. Each will be surrounded by L1 caches and the whole group is connected with the L2 and the outside. This will shrink the interconnect delay within a group relative top process size and thus keep the appropriate balance between clock and functionality that is assumed by the paper's authors to go out of whack. Lets face it, doubling the cache size will begin to be diminishing returns as the latency increases due to those interconnect delays. Adding new levels of cache and making logic neighborhoods will allow for more logic/memory to be packed into a die and still keep the clock gains and performance gains. This is what a Hammer DCDC (Opteron dual core) does. It gets two cores on say 90nm and larger L2 on the die, but still gets a 40% clock increase and a 2.8 times the overall performance over 130nm Opteron DCSC with no loss due to interconnect delay. At 65nm, Opteron QC (quad core) gets 2 times the clock of Opteron 130nm and 8 times the performance all on the same die. Good reason to keep that glueless CPU interconnect don't you think? Die stays the same but the performance more than doubles with each process shrink. Far better than just doubling the cache for what, a 1.5 times performance of the old die? Pete