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To: Jim McMannis who wrote (164656)4/28/2002 12:41:02 PM
From: Elmer  Read Replies (1) | Respond to of 186894
 
I was looking for a yield number. Since NO ONE here really knows Intels yields I really didn't expect anything but a round about answer at best but all we seem to get is an AMD put down or a "heheee, yeah I know but can't tell you".

You still don't get it. There is no such thing as a "yield number" because it varies with die size. There is only defect density which is constant across die size. It's been explained to you over and over again and you just keep saying, "Oh! OK, but what are Intel's yields?". Since there are several people here who know exactly what Intel's defect density is, and what their yields are, I'll answer your yield question. Intel's yields are 35.5%, 37%, 38%, 47%, 51%, 66%, 71%, 88.8% and 94%, plus a few more in between.

Satisfied?

EP



To: Jim McMannis who wrote (164656)4/28/2002 5:19:44 PM
From: tcmay  Read Replies (1) | Respond to of 186894
 
"I was looking for a yield number. Since NO ONE here really knows Intels yields I really didn't expect anything but a round about answer at best but all we seem to get is an AMD put down or a "heheee, yeah I know but can't tell you".
On the other hand, seems rather interesting that Intel can get "world class" yields on 300 mm wafers at .13u and no one else can get .13u to work well.
AMD seems to have hit a rock wall again. After fabing chips for many years you'd think they would know what Intel knows..."

It's been explained to you that the "yield = percentage good" notion is a flawed way of looking at things. The probability of a die being good is the probability that it has no defect (no significant defect, a subtle point we won't get into here...clearly there are many types of defects, and not all of them are chip-killers). The probability that a die has zero defects is given approximately by the Poisson distribution, which gives the number of things have 0 defects, 1 defect, 2 defects, 3 defects, and so forth. The probability of seeing m defects given that s are "expected" is given by:

P (s;m) = ( exp (- m) * m^s ) /s!

So if a die is "expected" to have, say, 1 defect (total number of defects divided by total number of dice), then the percentage of dice with zero defects is:

P (0; 1) = ( exp (- 1) *1^0 ) /0!
= 1/e
= 36.7%

Since yield is the case where s = 0, we can replace the general Poisson equation with:

Y = yield = P (0;m) = ( exp (- m) * m^0 ) /0!
= exp (-m)

The value m above is linearly dependent on area, of course, but exp (- m) is of course _not_ then linear in area.

And so on. It really _is_ useful to get our your calculator and play with this formula for at least 10 minutes or so. (I played with it for many hours, and programmed it into my earliest programmable calculator, then my HP computer, etc.)

If you insist on a "Show me the yield!!" mentality, a little birdie told me that the key process _would_ yield 680 good devices on a wafer...if the dice were 100 mils on a side and the wafer were 2 inches in diameter. You should be able to back out certain things about yields from this.

--Tim May



To: Jim McMannis who wrote (164656)4/28/2002 8:20:18 PM
From: Gordon Hodgson  Read Replies (1) | Respond to of 186894
 
Jim, Re: "On the other hand, seems rather interesting that Intel can get "world class" yields on 300 mm wafers at .13u and no one else can get .13u to work well."

Here's something interesting... Intel has spent about 20 billion on R+D since 1994. Are you getting the clue now?