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To: Ali Chen who wrote (78663)	4/29/2002 11:15:50 AM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Ali: How do you figure that the same layout increases the interconnect delay. Signal propagation occurs at a constant velocity. A 37.5 million transistor CPU on 65nm has a signal length of 1/2 that of the same 37.5 million transistor CPU on 130nm. Thus, relative to a clock twice as high for 65nm as 130nm, the percentage of total signal delay for interconnect stays constant. Of course you have an explanation for why this is not so. Do not make the mistake of comparing a 150 million transistor design on 65nm to one using only 37.5 million on 130nm. Using only the transistors for the core plus L1 actually makes even more sense. For the Athlon that is about 24 to 25 million. If you also lose the L1 cache, the transistor count shrinks to 12 to 13 million. An increase to 512KB L2 from 256KB will naturally increase the transistor count to about 50 million. But, that little affects the clock speed of the core. The only major effect is the speed and latencies of the L2. Now justify your assertion that signal delays over half the length of that on 130nm on 65nm will not be one half of that on full length on 130nm. This is what occurs when you use the same design at a smaller process. Otherwise, you fall in to the same traps as those caused by the assumptions made by the paper's authors. And that leads you top the same wrong predictions. Pete