Notebook processors sizzling, and that's a problem
By Bruce Gain
EBN
(05/01/02 12:52 p.m. EST)
The popularity of mobile computing platforms is hastening the day when microprocessor designers will need to address mounting thermal issues that are accompanying the industry's drive toward ever-faster CPUs.
Once a topic of academic debate in the desktop computer sector, growing sales of notebook PCs, PDAs, and other handheld electronic devices are moving the matter of heat dissipation off the back burner.
Mobile-processor suppliers say they are prepared to accept the challenge, which is expected to arise with the advent of 5GHz chips that consist of 300 million or more transistors and are manufactured on 90nm-and-finer linewidths. Among the array of solutions are techniques like clock gating, dynamic frequency scaling, new IC packaging, and the use of larger on-chip caches that designers say will allow CPUs to consume a respectable 3W of power or less through 2004.
Without new methods for curbing thermal loss, current processor architectures employed on 90nm processes could yield chips for a typical notebook that would consume an average of 50W or more, according to analysts.
“It's one thing to have low power, but if you can't do anything with it to [accommodate] very high processor speeds, what use is it?” asked Shekhar Borkar, an Intel Corp. fellow and director of the company's Circuit Research Lab in Hillsboro, Ore. “Life was relatively easy following Moore's law until now, because of the [dissipation issue]. Because it is unthinkable to raise power [consumption], we're having to employ fundamentally different technologies to keep the power down.”
One supplier that has tried to make low-power technology a cornerstone of its business is Transmeta Corp. The Santa Clara, Calif., processor designer counts its low-power CPU technology as a strength not shared by Intel and other x86 processor vendors.
“Despite claims being made by Intel and others, I think you're going to have these [high-speed] processors in notebooks running at an average of 30W,” said Frank Priscaro, Transmeta's director of brand development.
Exploring the options
To maximize clock speeds at a given power level, processor makers are minimizing the number of transistors that are required to switch on or off at the same time, a technique known as selective gate switching, said Linley Gwennap, an analyst at The Linley Group Inc., Mountain View, Calif.
“This can be done by keeping the micro-architecture simple, such as using a short pipeline, and not wasting energy on things that don't compute results, such as branch prediction and speculative execution,” Gwennap said.
A problem with this technique, however, will involve binary compatibility in x86-based processors, Gwennap said. “Increasing performance with the x86 architecture requires more power than using a new, more efficient architecture,” he said. “That's why non-PC mobile devices use ARM or some other RISC or VLIW architecture.”
In a similar vein, chipmakers are looking at dynamically scaling the processor's voltage and frequency to meet varying performance demands, said Brett Tischler, a senior silicon architect at National Semiconductor Corp., Santa Clara.
However, dynamic frequency scaling still poses challenges depending on what type of and how many applications a particular computing device is running, said Lisa Su, director of emerging products at IBM Microelectronics, East Fishkill, N.Y.
“When you try to implement these things without having to stop the applications, it's a challenge. It's easier to do this by shutting the whole processor down,” Su said. “Truly doing it dynamically is difficult. With the PowerPC architecture, we have accomplished this by separating different voltage islands on the chip.”
Instead of expanding processor power by adding more transistors, Transmeta uses software to gain incremental performance increases-a technique also employed by the likes of Intel and Advanced Micro Devices Inc. Transmeta's new Crusoe processor line, with a 1GHz clock speed and an average power consumption of 1W, will use software that shuts down parts of the processor not in use when it is rolled out later this year, according to Priscaro. Last month, Toshiba Corp. launched a 2.4-pound notebook based on Transmeta's 800MHz processor with a battery life of 4.5 hours.
Architecturally, chipmakers also are developing techniques to offload more functions onto the cache memory to cut power by reducing off-chip signal output. “Cache is not expensive because it's based on CMOS and offers one of the most efficient power-reducing techniques,” Intel's Borkar said.
Indeed, chip-to-chip communication consumes more power than almost anything that is done on the chip itself, according to Gwennap.
“Cache memory helps by keeping most memory accesses on-chip, but the cache must be designed carefully so that only one bank is active at a time,” he said. “This reduces performance vs. the traditional method of powering all banks and throwing away the results you don't need, but tradeoffs must be made to save power.”
The promise of packaging
Once the processor meets power consumption specifications, however, further engineering will be required in the area of chip packaging. Newer technologies, such as flip-chip packaging that mounts the chip face-down on the substrate, will become a mainstay once processors host 300 million or more transistors, according to analysts.
Additionally, new substrates will have to be synthesized to accommodate the proliferation of transistor counts, said Nozad Karim, senior director of application engineering and electrical, mechanical, and thermal characterization at Amkor Technology Inc., West Chester, Pa.
“As additional heat dissipates down through the packaging, we're looking for better substrate designs to improve thermal conductivity,” Karim said. “To do that, we're looking at thermal enhancement capabilities that will offer heat spreading.” |
