Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (79795)	5/8/2002 5:28:58 PM
From: Charles Gryba	Respond to of 275872

Joe, the solution to that would be a large cache on the HT silicon, weren't we all talking about that a while back? C

To: Joe NYC who wrote (79795)	5/8/2002 5:31:11 PM
From: combjelly	Read Replies (2) \| Respond to of 275872

"Wouldn't HTT-like memory interface suffer from latency penalty" Why? All of these interfaces, DRDRAM, SDRAM, DDR, DDRII are all interfaces to the essentially unchanged DRAM core from the 1970's. DRDRAM gets an awful lot of it's latency because of it's otherwise clever daisy-chain scheme. It has to allow for the signals to propagate through the arrays and back again. HTT used as a memory interface would have the problem that it would be inherently shallow, i.e. it's point to point. But there wouldn't be the propagation delays because of this either. It would also have the nice property that as you add memory, your bandwidth goes up. It's downside is that your memory expansion is limited by the number of HTT ports, so for very large memory arrays, you would need to have HTT switches that would add some to the latency.