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To: TGPTNDR who wrote (80379)	5/21/2002 5:11:23 AM
From: ptanner	Read Replies (1) \| Respond to of 275872

re: "But now it is fabrication that dominates yield, not defect density." Could someone explain the difference? TIA, -PT

To: TGPTNDR who wrote (80379)	5/21/2002 1:44:32 PM
From: semiconeng	Respond to of 275872

TSMC's Sheng put the bottom line succinctly: "For an average fabless semiconductor customer using our 300-mm line, a wafer lot is anywhere from three to seven wafers." Seems there's not a lot of wafers in a wafer lot these days. --- Maybe for a Foundry, For others, a lot is 25 wafers. Our whole approach was based on the assumption-true so far-that chip failures were dominated by defects," Billat explained. "But now it is fabrication that dominates yield, not defect density. This will require us to forge a link between design and test. Somebody should be telling Yousef about this concept -- but I'm not the one. --- Pure B.S. Just what I would expect from a "Marketing Manager". Process Engineering on the other hand knows that Defect Density drives Die yields. Just as Yousef says. Also, the industry must put more funding into 3-D structures, in which logic devices, memory, sensors, and chip-to-chip optical interconnects would be stacked and connected vertically in a single package. Looks like this guy thinks basic physics isn't going to be a problem for a while, but there will have to be some difficult process engineering and design work. tgptndr --- Intel is already using a stacked design with StrataFlash. Other devices are only a matter of time. Semi