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To: Elmer who wrote (80515)	5/22/2002 11:36:01 PM
From: ptanner	Read Replies (1) \| Respond to of 275872

Elmer, re: "It sure isn't manufacturing cost." What portion of the cost would you guess is fixed versus variable? As the P4 shifts to 0.13 it would seem reasonable to use the 0.18 for the next Celeron unless there are other products which could yield greater value from the 0.18 facilities. This "trickle down" of facilities is an advantage that Intel has over AMD - what happened to the 0.25 equipment in Fab 25 and the 0.18 equipment in Fab25 and Fab30 as they shift to 0.13? The salvage value has got to be pretty poor compared to the option of using it in place for a comparable product. I am curious about whether the P4-Celerons will be the same size as Willamette (ie. disable half the cache?) or if it will be a revised layout. The size of the cache is modest relative to the overall die so might not be worth the cost of revising. -PT

To: Elmer who wrote (80515)	5/22/2002 11:45:06 PM
From: wanna_bmw	Respond to of 275872

Elmer, Re: "Intel is pushing a much larger die on an older process for the lowend market. Why if not for marketing reasons? It sure isn't manufacturing cost." It's probably because they can't ramp .13u production all at once. It's too big of a risk. And meanwhile, they want to transition to Northwood over Willamette very quickly in the mainstream markets to increase margins, while transitioning to socket-478 Celerons in order to promote a common platform. On the manufacturing side, they change Tualatin-256 wafer starts into Northwoods, thus increasing that ramp; meanwhile, they transition Willamette to Willamette-128, which takes care of excess .18u capacity. The fact that megahertz can sell itself allows the plan to work. wbmw