<font color=red> Preliminary Conference Agenda
Tuesday, July 16
8:30 - 10:00
Keynotes
PCI Special Interest Group
Samsung Semiconductor Inc.
Advanced Micro Devices
VIA Technologies, Inc.
NVIDIA
10:00 - 11:30
Power Panel
64-bit Platform Solutions
Moderated by Nathan Brookwood, Insight 64
Panelists: AMD, Sun Microsystems, HP, (TBA)
Power Panel
Directions for Main Memory Technologies
Moderated by Sherry Garber, Semico Research
Panelists: Samsung, Denali, Elpida, Infineon, AMD, Rambus
11:30 - 12:30
Blade Server Strategies
This session will focus on high-density IA-32 server strategies and will consider the technologies, trends and
standards, which are driving the evolution of these platforms. Understand how new core logic integration and
positioning strategies will impact your next generation designs. Examine interconnect and peripheral I/O
alternatives, preferred DRAM choices and microprocessor strategies.
Designing A Thin & Light Notebooks with Athlon XP
The notebook market is growing faster than the total PC market, with the Thin & Light market segment growing
the fastest. In this session you will see how to take advantage of the Athlon XP processor to design a
high-performance power-managed Thin & Light notebook platform. The discussion will include design tradeoffs
on graphics, power management and battery life, and thermal design, including how to leverage the Athlon
System bus for performance and low power consumption.
Design Strategies for Next-Generation Small Form Factors Platforms
Wireless bandwidth is increasing faster than the ability of the devices designed to use the data. The next
generation of mobile information devices will need to provide PC-like performance and graphics resolutions
while operating within ever decreasing power consumption and form factor constraints. A critical need for the
right combination of price, performance and power requires tight integration between component selection,
system design, physical design and software design. This session will address the system design
requirements and offer strategies for building this next generation of full-featured mobile devices.
PC Memory Solutions
Abstract Pending
12:30 - 1:30
Lunch
1:30 - 2:30
System I/O Modularity for Highly Differentiated IA-based Servers and Workstations
This session will describe the latest Reliability, Availability and Serviceability (RAS) features of advanced core
logic for server and workstation platforms from entry-level to enterprise class including support for DDR
memory and PCI 66, 133, 266 and 533.
Keeping I/O Up to Speed -
Tomorrow's processors and I/O devices demand much higher bandwidth than today's chip interconnect
standards can deliver. HyperTransport, RapidIO and PCI-Express are the leading prospects for next
generation interconnect. This session will compare capabilities and system applications of these I/O
standards from a physical layer specification point of view.
DDR-SDRAM, FCRAM, and RLDRAM:
A Platform Approach To High-Performance Memory Systems -
Memory is now the key performance bottleneck for a wide variety of applications from PC and servers to
communications and consumer electronics. Keeping processors fed with data is further complicated with the
diverse set of bandwidth/latency requirements for these applications. Denali addresses the complete process
for memory system development, from memory selection and memory controller design, to system
performance analysis and physical implementation. Configurable semiconductor IP cores for memory control
and bandwidth allocation will be examined as a key to achieving memory performance targets for a wide variety
of applications.
Hyperthreading and DRAM -
An analysis of the relationship between server scalability and memory bandwidth in a 3-tier web application
environment. Using data obtained during testing of various Intel Xeon DP-based server platforms, CSA analysts
will explore the impact of memory subsystem design on the performance of CPU-intensive, multithreaded
workloads as executed against a Simultaneous Multithreading (SMT - a.k.a. "Hyperthreading") CPU core.
Includes discussion of test methodology and future directions for various server memory architectures.
Mobile Memory Solutions
Abstract Pending
2:30 - 3:30
Computing by the Slice:
Separating Myth from Reality in the Emerging Server Blade Marketplace
A discussion of the myriad price/performance hurdles faced by IT shops as they evaluate first generation
Server Blade solutions. Includes a discussion of real-world performance and cost of deployment vs. traditional
Standard High Volume (SHV) Intel-based server solutions. Attendees will leave with a better understanding of
how first generation Server Blade solutions stack up today and also which emerging technologies will help
drive the adoption of Blade Computing concepts in mainstream data center applications.
The Challenge of AGP 8X
With the developing trend in CPU and DRAM, wider system bandwidth requirement has been the continuously
driving force in PC. AGP 8X, the upgrading path from AGP 4X and with 2GB/s bandwidth, can meet the
bandwidth requirement for the next 2 years. However, there are still some challenge in designing an AGP 8X
PC system. This section is to explore the mystery of AGP 8X, and how to design a good and stable AGP 8X
graphic card. The related timing and layout will be discussed.
DDR / DDR II System Design Guide
Back by popular demand, this session will present the latest updates and design issues related to DDR and
DDRII SDRAM. The main topics covered will be:-- Initialization- Board design- Signal Integrity evaluation-
Thermal issues.
Motherboard designs for IA-based Server Platforms
A host of new motherboard designs are currently available for IA-based server. These ready-made platforms
can save time and cost associated with building systems from scratch, yet they also offer the latest
technology for building high-peformance, high-bandwidth integrated system designs.
FLEXFITTM Universal Platform Architecture
An Innovative Approach To Computer Design - Today the computer designers have an unprecedented
challenge of designing ever growing diverse product portfolio with shrinking engineering resources and shorter
development cycles and at the same time controlling the engineering investment and support costs.
FLEXFITTM Universal Platform Architecture solves the problem through an innovative modular architecture,
leveraging a universal platform, to easily build an entire product line to offer economical, TTM, diverse product
portfolio with lower support cost and lower TCO.
3:30 - 4:00
Ice Cream Break
4:00 - 5:00
Exceeding Your Limits With DDR400 - A Whole New Meaning For Performance
The PC market in this era has unlimited need for ultimate speed, bandwidth, and flexibility. The general
reflection can no longer satisfy the instant need for trend. With plenty years of experience in the technology
integration of chipsets, SiS is confident in providing the most cutting edge solutions. And the most intimidating
one of all, is the support to DDR400. In this session, SiS will present the technical overview of DDR400
technology. Including features and benefits, implementation strategies, and product roadmaps.
Graphics Power Management for Notebook PCs
Today's Mobile PCs are equipped with features rivaling those of high-end desktop systems, with the attendant
power consumption challenges. Wireless connectivity and new form factors will further drive the need for
longer battery life. This session will present an overview of power management from a graphics perspective and
detail system design approaches and recommendations to optimize battery life.
Super Low Power DRAM for Mobile Applications
This session will review the latest advancements in self refresh technology for DRAM memory subsystems
optimized for low power, mobile applications.
AMD Assured Program - Commercial Solutions for the Rest of Us
This session will provide an overview of commercial platform requirements, and the AMD Assured program.
AMD and ASUS will be presenting a solution that has been created specifically to provide commercial class
motherboards for the system builder community. AMD Assured motherboards are defined to provide network
manageability, product stability and long-tem availability. The session will include an overview of the AMD
Assured product portfolio, and will focus on how systems builders can create commercial solutions that are
competitive with the "big guys".
Serial ATA, Enabling the future of high performance, low cost storage solutions -
Learn the nuts & bolts of Serial ATA (SATA), as well as, the benefits of integrating this innovative interface into
high performance desktops, NAS and small form factor PCs. Explore the differences between SATA 1.0, 2.0
and the enterprise interface of the future, Serial Attached SCSI. Integrating Serial ATA drives can improve your
overall system reliability by improving airflow and data reliability, as well as, improved performance now and for
the future. Serial ATA is 100% software compatible with lower voltage requirements and improved power
management.
6:00 - 7:00
Evening Mixer
Wednesday, July 17
9:00 - 10:30
Power Panel
Where Does I/O Go From Here?
Moderated by Nick Stam, Ziff Davis
Panelists: PCI SIG, ServerWorks, HyperTransport Consortium, Rapid I/O TA
Power Panel
Making the Most of the Small Form Factor Opportunity
Moderated by Bert McComas
Panelists: Transmeta, VIA, NVIDIA, AMD
Power Panel
The Future of Graphics: Trends, Technologies and Strategies
Moderated by Jon Peddie, JPR, Inc.
Panelists: NVIDIA, ATI, 3DLabs / Creative Labs, SiS, VIA
10:30 - 11:30
PCI Express™ (formerly 3GIO):
A Low Cost, High Performance, Scalable I/O Technology for Computing and
Communications Platforms
This session will provide an architectural overview of PCI Express and describe the technical details for the
PCI-SIG's newest industry standard specification. PCI Express is a serial I/O technology that is compatible
with the current PCI software environment. It defines a packetized protocol and a layered architecture that
enables attachment to copper, optical, or emerging physical signaling media. PCI Express provides higher
bandwidth per pin with low overhead, low latency and embedded clock architecture. It can be used as a
unifying I/O architecture in multiple market segments, as chip-to-chip and add-in card applications to provide
connectivity for a variety of performance-intensive applications such as next generation graphics, and as an
attach points for other interconnects like 1394b, USB 2.0, InfiniBand and Gigabit Ethernet. Its initial bit rate is
defined as 2.5 Gigabits per second per lane per direction. PCI Express provides superior bandwidth scalability
in both frequency and interconnect width, and defines advanced features such as reliability, Quality of Service,
Isochronous data delivery, power management, hot plug and hot swap, multi-hierarchy, advanced switching
support as well as innovative form factors suitable for all computing and communications platforms.
DDRI/DDRII Power for Dummies -
Through state diagrams and architectural block diagrams, Infineon's presentation will provide a detailed look
into the various current values specified by a DDR DRAM, along with highlighting the differences between DDRI
and DDRII. A comprehensive exploration into the contributors of the various standby, operating, and refresh
currents, as well as the relationship between voltage, frequency, and density will take place.
HyperTransport Technology: A Tutorial -
This presentation describes some of the keep features of the HyperTransport bus architecture and shows you
how to use this bus as an interconnect bus for processors as well as peripheral devices. HyperTransport is a
high-speed (800MHz), high-bandwidth (12.8 Gbytes/s, scalable performance, dual simplex point-to-point
interconnect bus The presentation describes electrical and protocol basics of the architecture. Protocol details
include description of packet type, transactions flow, flow control and the concept of virtual channels.
Small Form Factor Platforms -Watts Up doc! -
This session will address AMD's response to the growing SFF Market. We have been successful with our
strategy in the Japan market, but as PC's become more ubiquitous in our everyday lives, we find a need for
smaller, less intrusive computing solutions in both consumer and commercial applications. This session will
provide an update on AMD's CPU and platform initiatives to enable the smallest, high-performance desktop
computer systems in the market.
11:30 - 12:30
PCI-X 266 and PCI-X 533:
High Performance Local Bus for Future Server and Workstation Platforms -
The PCI-X 2.0 specification is a high-performance extension to the PCI Local Bus specification that facilitates
connections to add-in cards for 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, Serial Attached SCSI, Serial
ATA (SATA), 4X and 12x InfiniBand, RAID and cluster interconnects for servers and workstations. PCI-X 2.0
defines two new versions of PCI-X add-in cards: PCI-X 266 and PCI-X 533. The first, PCI-X 266 runs at speeds
up to 266 MegaTransfers per second using Double Data Rate (DDR) techniques, enabling sustainable PCI
bandwidth of more than 2.1 Gigabytes/second. PCI-X 533 runs at speeds up to 533 MegaTransfers per second
using Quadruple Data Rate (QDR) techniques enabling bandwidth of more than 4.3 Gigabytes/second. The
specification also provides increased reliability through Error Checking and Correction (ECC). PCI-X 2.0 will
provide customers with needed I/O bandwidth along with investment protection because of its backward
compatibility with existing systems. This session will provide a detailed overview of the benefits of
implementing PCI-X into current designs.
HyperTransport Technology: A Tutorial -
This presentation describes some of the keep features of the HyperTransport bus architecture and shows you
how to use this bus as an interconnect bus for processors as well as peripheral devices. HyperTransport is a
high-speed (800MHz), high-bandwidth (12.8 Gbytes/s, scalable performance, dual simplex point-to-point
interconnect bus The presentation describes electrical and protocol basics of the architecture. Protocol details
include description of packet type, transactions flow, flow control and the concept of virtual channels.
Memory Choices for OC-192 Applications -
To support OC-192/10Gbps line rates, leading-edge networking equipment needs high performance memory
subsystems to buffer and process the incoming data packets. The memory solutions must meet demanding
performance, quality of service (QoS), power, and space requirements. This presentation will evaluate and
compare RDRAM, DDR and other memory technologies for advanced network applications.
Designing Next Generation HyperTransport Based Systems -
This presentation focuses on the bandwidth needs of next generation embedded and computing systems and
analyzes why HyperTransport IO technology is becoming a key ingredient in these systems designs. The
presentation also outlines the family of HT based chip-to-chip interconnect from SiPackets and how it expands
the possibilities for today’s system architects and designers by providing them with design options based on
HT and other industry standard networking and IO interconnect technology never before possible.
12:30 - 1:30
Lunch
1:30 - 2:30
Memory Design Considerations That Affect Price and Performance-
What makes DDR-I at 400 MHz a boutique part when DDR-II at 400 MHz will be a mainstream standard?
What is different about these devices and the system infrastructure to support them that makes one easier to
design than the other? This discussion will review the industry standard DRAM roadmap, and examine the
similarities and differences between the next two generations of standard DRAMs. Then we will focus on how
controller designers can best exploit the differences and plan for the transition from DDR-I to DDR-II.
Quad Data Rate PCI-X 2.0 Design Guide -
PCI-X 2.0 leverages heavily from PCI-X 1.0, many elements of the design remain the same: architecture, state
machine, signals, layout, connector, etc. However there are also new elements that must be considered:
strobes, ECC, new registers, new I/O buffers, signal termination and turn-around. Of particular interest is the
challenge of getting to 533 MByte data speeds. This session will discuss new features and how they are
utilized to achieve the higher speeds of PCI-X 2.0. This session will also touch on the practical applications of
PCI-X 266 and PCI-X 533 in adapter cards.
Designing For Debug, Validation and Compliance Testing -
A HyperTransport link provides a robust high-speed architecture with an easy to implement protocol stack. As
this technology continues to rapidly gain acceptance across a variety of industries designers need to be able
to communicate with a variety of other bus topologies, such as PCI, PCI-X, PCI Express and InfiniBand.To
insure the successful integration of this wide variety of buses it is not enough to just get a single
HyperTransport link working. It is also critical that the link meets the specifications defined by the member of
the HyperTransport Consortium, that the link is operating at its maximum efficiency, and that it is able to
communicate with other bus technologies.
HyperTransport Networking Extensions -
The HyperTransport Consortium recently announced a series of extensions to the HT I/O Link protocol. This
talk will explain the use of applications in networking extensions.
HyperTransport: Why Its Good For the Industry
2:30 - 3:30
Migrating from PCI-X 1.0 to PCI-X 2.0 -
This session will consider design methodologies for migrating PCI-X 1.0 design to PCI-X 2.0. Many elements
from PCI-X 1.0 can be leveraged in PCI-X 2.0 implementations. This session will examine the similarities and
changes to form factors, protocols, connectors, signaling, BIOS, device drivers, etc.
HyperTransport Based AMD Opteron Processor:
This session will provide an overview
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