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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: StanX Long who wrote (64318)	6/12/2002 12:36:42 AM
From: StanX Long	Read Replies (1) \| Respond to of 70976

Technologist sketches IBM's silicon road map By David Lammers EE Times June 11, 2002 (6:32 a.m. EST) eet.com HONOLULU — As chip makers find it increasingly difficult to wring higher performance from silicon while maintaining acceptable power consumption levels, IBM Corp. plans several major changes to its CMOS recipe over the next five years, said Bijan Davari, vice president of technology development at IBM Microelectronics. Speaking prior to the start of the 2002 Symposium on VLSI Technology here, Davari said IBM plans to be aggressive about the introduction of strained silicon, and to build upon that foundation to later introduce a high-k gate dielectric and vertical dual-gate transistors. With its internal server division and external ASIC customers hungry for the highest performance devices, IBM technologists have made advances in several key areas over the past decade, including utilization of copper interconnects, silicon-on-insulator (SOI), silicon germanium BiCMOS, and low-k dielectrics. Not all of the company's initiatives have paid off. IBM invested billions of dollars in X-ray lithography before abandoning those efforts. But IBM has been right often enough for Davari to claim that competitors have "followed our road map to a T." Davari said IBM plans to introduce strained silicon technology at the 65-nm technology node, which is expected to see its first introduction in 2005. Strained silicon takes advantage of the phenomenon that electrons have higher mobility when a thin layer of silicon is deposited on top of a thicker, graded layer of silicon germanium (SiGe). The larger crystalline lattice of SiGe exerts a strain on the thinner top silicon layer, stretching the silicon lattice slightly. IBM plans to create the graded SiGe layer, and the top active layer of silicon, on an SOI substrate. Strained silicon will improve electron and hole mobility significantly, but adds complexity to CMOS processing. One challenge is avoiding damage to the top silicon layer, which is 400 to 500 Angstroms thick. Another is grading the SiGe layer with the right mix of germanium atoms.