Process issues push into 90-nm design flows
By Ron Wilson
EE Times
(07/09/02 15:10 p.m. EST)
SANTA CLARA, Calif. — Each new process node brings its own set of challenges for the design flow, and the 90-nanometer node is about to deliver a whopper. So says Craig Peterson, co-general manager of Intel Microelectronics Services, the ASIC arm of Intel Corp. "All of these effects have always been present in CMOS processes, but with each new node new effects become significant, and have to be accounted for in the design process," he said.
Peterson listed seven categories of effects that originate in process technology and that, by the 90-nm (0.09-micron) process node, will have a direct impact on the design flow. Process technology itself, increasing complexity, spiraling performance as measured by clock frequency, power dissipation, component density, reliability and design productivity make up the seven categories.
To illustrate his point, Peterson dug deeper into just the question of process-related issues. "In quarter-micron processes we saw a big discontinuity in design because for the first time we had to consider RC effects in the interconnect," he said. "The simple models didn't work any more, and timing closure became a big issue. Delay modeling had to move to the front end of the design flow — it merged into floor planning and synthesis."
Then, at 0.18 micron, Peterson continued, signal integrity first reared its gruesome head. "Suddenly the dominant parasitic capacitance on an interconnect line wasn't to the substrate anymore, it was to adjacent signal lines." Unfortunately for the unwary, signal integrity problems have been sufficiently elusive that not every design shop even recognizes that they exist. "Part of the problem is that conventional stuck-at testing doesn't reveal marginal signal quality," Peterson warned. "And often it only shows up at process corners that the foundry will only reach as edge rates improve with time. So the problem may be there, latent in a design, but show up as field reliability data, not as test dropouts. This has allowed a lot of people to stay in denial. But if we run signal integrity examination tools on the design, maybe we will find a dozen violations in a typical 0.18-micron design."
Further, power started to become an issue at 0.18 micron. "If you push performance, you undo the power gains that you achieved by dropping the operating voltage. Worse, with the lower voltage, you are pushing a lot more current, and now IR drops in the power grid become very significant issues. They have to be accounted for early in the design — either minimized or modeled — to prevent surprises in the behavior of the logic."
Added issues
At 0.13 micron — a process node that Intel is currently making available to its ASIC clients — three more issues add to those previously listed, according to Peterson. But he emphasized that the old issues stayed around, and sometimes got worse. "In signal integrity, for example, where on a typical 0.18-micron design we might see a dozen violations, at 0.13 micron we are typically seeing around 300 violations. There are too many of them to deal with downstream — they need to be avoided by correct early design."
The three new issues are equally significant. First is the widely discussed problem of static leakage current. Second, contrary to much of what has been said in the industry, in-die variations, especially in clock trees, are already becoming an issue at 0.13 micron. Peterson warned that variations in either transistor gate dimensions or in interconnect across a die have been observed to cause significant clock skew problems on 0.13-micron dice. Third, Peterson declared that soft errors — currently a hotly debated issue — are in fact an observable problem in existing 0.13-micron processes. Worse, the problem impacts not just SRAM cells — where solutions are well understood and in use — but logic flip-flops as well, where new design techniques are necessary to achieve long-term reliability.
In summary, Peterson made two points. First, perhaps the most worrying problem with any of these process nodes is the tendency of design teams and ASIC vendors to go into denial rather than diagnosis. "It's genuinely scary that some people are claiming there are no signal integrity problems at 0.18 [micron]," Peterson said. "Maybe process problems or defects are getting blamed, but there are very real signal integrity issues at this node, and if you don't deal with them they will find you."
Further, he pointed out that the only successful way to deal with the gathering layers of new issues was to incorporate changes into the early stages of the design flow. "For instance, we know that we are seeing problems with feature formation in foundry processes. That has to be dealt with early — we do it in the floor-planning stage — not with fixes at the end of the physical design flow. That means beginning to think not just about functional blocks and netlists, but about interconnect layers and via densities in floor planning, not waiting until detailed routing."
Peterson also suggested that Intel had a fortunate perspective on these issues. "While we are making 0.13-micron foundry processes available to our customers, we have available to us the data from our own process engineers, who at this point are working on proprietary 90-nm and 65-nm processes," he said. "So we can not only see what the CPU folks experienced when they were at the 0.13 node, but what we will be facing in the future as well." |
