Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dumbmoney who wrote (85345)	7/18/2002 9:07:20 PM
From: Win Smith	Respond to of 275872

But the Hammer CPU is meant to be used that way in normal operations, at least in multiprocessor NUMA configurations. There was a line somewhere recently where an AMD spokesperson said the latency of a memory access through an adjacent cpu on the Hammer was about the same as the latency in a convention CPU - chipset memory access. Not that it would be optimal to leave the onboard controller unused. On the other hand, I think the DDRII issue is somewhat overblown, by past experience those memory generation turnovers aren't instantaneous.