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To: Yousef who wrote (86281)	8/2/2002 2:02:50 PM
From: Ali Chen	Read Replies (2) \| Respond to of 275872

"I really don't expect much from you in "process expertise". ... More likely causes are subtle issues when integrating various process modules (etch/dep/CMP/Cleans/litho/...) together Some unintended interaction causes the yield problem." You really must think that only at Intel the people in manufacturing are God gifted and immensely talented, and rest of the world is stuffed with round idiots. I think all your posts here are the proof that it is not true. Even the opposite is likely. - Ali

To: Yousef who wrote (86281)	8/2/2002 2:07:34 PM
From: semiconeng	Respond to of 275872

Re: "What do you expect from me, a process qualification dissertation ..." I really don't expect much from you in "process expertise" ... That's why I was "correcting" you about your faulty statement. Yield problems usually are not due to a tool not meeting specifications. Tools meeting specifications are well monitored and technicians/engineers need to be "fired" if this is the problem. My toolset does a Daily Station Monitor, and a Weekly Station Monitor. Plus there is Weekly and Monthly Preventative Maintanence performed on the tool. In addition, there is Dynamic, Tool Processing Parameter Excursion Protection, on all of the Layers, which Monitors the Tool's Processing Parameters, while the wafers are being processed. Trust me, If there is something wrong with one of my tools, or it's not operating within it's Process Window, I find out about it, usually while the wafers are still processing on the tool. Semi