Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Novellus -- Ignore unavailable to you. Want to Upgrade?

To: Kirk © who wrote (3378)	8/21/2002 9:39:23 PM
From: SemiBull	Read Replies (1) \| Respond to of 3813

Executive Comment: Richard Hill, chairman and CEO of Novellus By Richard S. Hill, Semiconductor Business News URL: siliconstrategies.com The following contributed article was provided to SBN by Richard Hill, chairman and CEO of Novellus Systems Inc. The San Jose-based company is one of the world's largest suppliers of semiconductor equipment. In the fast-paced semiconductor industry, technology changes can quickly elevate a manufacturing process that was perceived as minimal or low value to one that is critical. This happened in recent years with chemical mechanical planarization (CMP), and now, it is happening now with surface preparation. Surface preparation today is a new ballgame. Extensive experience with copper damascene manufacturing shows that proper surface preparation is key to successfully building the advanced interconnects required for today's most powerful devices. An experienced housepainter knows that an improperly prepared surface will not hold paint for very long. Similarly, process engineers know that improperly prepared film surfaces in a copper and low-k interconnect structure will lead to a degradation in device performance. In the damascene manufacturing process, it is the softer dielectric film, rather than the metal film, which is etched. Etching low-k dielectrics, in particular, requires new techniques, which, in turn, places an increased emphasis on surface preparation. The goal is to be able to selectively clean these softer and more porous materials effectively without damaging the deposited film. The resulting surface should be free of both polymer and photoresist residues, and the cleaning process should not result in shifts in the k-value of the dielectric film, changes in the interconnect critical dimensions (CDs), or undercuts or facets on the trench or via--all problems which may occur with improper cleaning. This transition to damascene processing has created a divergence in front-end-of-line (FEOL) and back-end-of-line (BEOL) strip and clean approaches. FEOL photoresist strip approaches have not changed significantly and continue to be done at about 250*C using an oxygen-based chemistry. Current FEOL strip and clean technology is expected to remain viable below the 0.10-micron node, with the primary drivers remaining tool throughput and cost of ownership. BEOL strip and clean in the presence of low-k materials however, requires a very different methodology. Typical low-k photoresist and residue removal requires different temperature and pressure conditions, as well as different process chemistries. These process variables must be optimized to ensure that the exposed low-k dielectric is cleaned in a highly productive and cost-effective manner with minimal damage. Based on our experience at the Customer Integration Center with copper damascene processing, Novellus has found that a low temperature, anisotropic process combined with the appropriate chemistry, effectively removes photoresist and residue, while simplifying the subsequent wet clean steps. Although the BEOL strip and clean can be done in an etcher, the cost of ownership associated with this approach is at least 25 percent greater due to the higher capital costs associated with complex etcher systems. New dry clean surface preparation technologies are key in ensuring optimal performance and manufacturing yields for devices incorporating copper/low-k damascene interconnect structures. Although several alternatives exist to address this issue--including the use of complex etchers--what customers will need in production ramps is the combination of the right technology and the right tool to meet the cleaning challenge.