This is ridiculous...........you are saying this news release was redone because of this significant new point that INTC is using "stressed silicon" in its new 90 nm processing. Personally, I doubt the use of "stressed silicon" is rocking the semi world to its foundations. But just in case, can you point out to me where they discuss in depth this remarkable new innovation............."stressed silicon". I have reread the article three times and can't find any mention of "stressed silicon". TIA.
First off, I think I've used the wrong term. I should have said "strained" silicon, and there have been so many discussions among the technicial publications over the last couple of days that even a blind man could find them with a simple search. Try this one for good technical content:
eetimes.com
HILLSBORO, Ore. — In a surprise move, Intel Corp. said Tuesday (Aug. 13) that it will add strained silicon technology to its 90-nanometer technology mix, and will use the process to make the Pentium 4 microprocessor code-named "Prescott" starting next year.
Intel's move at the 90-nm node sets up a head-to-head competition in the X86 processor arena between the silicon-on-insulator (SOI) approach taken by Advanced Micro Devices Inc. for its Hammer MPUs and the strained silicon approach of Intel for its processors.
Slight cost adder
Mark Bohr, director of process integration and architecture at Intel's development facility here, said Intel has developed a form of strained silicon that enhances drive current by 10-to-20 percent, while adding only 2 percent to the cost of a processed wafer. Intel has had strained silicon in development for roughly the past year, and will be the first company to move it into manufacturing, Bohr said.
"We have figured out a way of changing the silicon lattice structure to allow faster electron flow — a 1 percent change in silicon spacing to achieve a 10-to-20 percent increase in drive current. Intel is unique in that we can do this with no deterioration in terms of the short channel effect or junction leakage," the Intel fellow said.
Strained silicon takes advantage of enhanced carrier mobility through a silicon lattice that has been slightly stretched, or strained, thus making it easier for electrons to flow through the lattice.
Bohr declined to provide details of Intel's strained silicon approach. "We're in a very competitive industry and we don't want to help our competition," he said. Though Intel will provide more information about its overall 90-nm process in a presentation planned for the International Electron Devices Meeting in San Francisco this December, even then Intel won't say much more about its strained silicon technology, Bohr said. A more complete disclosure will come when products based on the strained silicon approach begin shipping sometime in 2003.
Intel is already using 90-nm technology at its 300-mm wafer development fabrication facility here for the trial manufacture of 52-Mbit SRAMs. The process will be used to build a Pentium 4 processor to be introduced in the second half of 2003, code-named Prescott, that will operate at more than 3 GHz.
Though Intel's specific approach remains closely-guarded, most companies using strained silicon grow a thin layer of active silicon on top of a thicker layer of silicon germanium. The larger germanium atoms strain the silicon lattice slightly, allowing higher mobility, particularly for the electrons used as carriers through the channel of NMOS devices.
PMOS devices typically operate more slowly than NMOS devices, and the imbalance usually worsens in strained silicon. Getting a commensurate boost in the PMOS devices has proven more challenging, and Bohr said Intel has figured out a way to achieve an acceptable balance between the NMOS and PMOS portions of its CMOS circuits.
To date, IBM Corp. has been the main proponent of strained silicon, with a plan to add its version of strained silicon to IBM's 65-nm process node, which is expected to move to first manufacturing in 2005. IBM plans to combine its strained silicon expertise with its silicon-on-insulator capabilities. However, IBM researchers have indicated at least a 10 percent cost adder for strained silicon, and said much work remains to balance the mobility enhancement in the NMOS and PMOS portions of a CMOS device.
Dan Hutcheson, president of VLSI Research Corp. (San Jose, Calif.), said "it is pretty clear that Intel has made a major breakthrough here. It is amazing that they would use strained silicon at the 90-nm node, and if the cost adder is only 2 percent then the process additions would need to be pretty trivial."
A processed 300-mm wafer might cost $5,000 at the finished manufacturing stage, and a 2 percent increase in processing costs would amount to only $100 or so, Hutcheson noted.
Increased drive current
Bohr said the use of strained silicon, and a gate oxide measuring only 1.2-nm thick, will support the faster circuits. The NMOS transistors have a drive current of 1.2 milliamperes per micron, while the PMOS devices are rated at 0.6 mA/micron — a significant increase over drive currents in the 130-nm process.
Intel also scaled the maximum operating voltage to 1.2 V, down from 1.4 V in the 130-nm process. Bohr said scaling the operating voltage has become more difficult with each process generation, largely because there are limits to how much the threshold voltage can be reduced. Reducing the operating voltage is key to keeping power consumption under control, and Intel is likely to operate its mobile processors and other power-sensitive products at around 1 V at the 90-nm node.
Intel also has reduced the gate length to about 50 nm, and will use 193-nm lithography for the four or five critical layers of a chip that include gate formation. Other than those critical layers, Bohr said Intel will stick with 248-nm lithography for its 90-nm process.
Also, Intel will move to a carbon-doped oxide for the intermetal level dielectric. The CDO low-k material will provide an 18 percent reduction in the overall k-value of the dielectric stack, which includes the insulator and etch stop barrier. For its 130-nm process, Intel used a form of fluorinated silicate glass with a k-value of 3.6.
The use of a low-k, the thinner gate oxide, and other moves were considered by analysts to be business as usual, while the adoption of strained silicon came out of the blue. "If they can do strained silicon with only a 2 percent cost adder, it's a slam dunk for Intel," said Rick Doherty, founder of Envisioneering, a technology analysis firm based in Seacrest, N.Y. "Perhaps Intel has found a process edge that IBM hasn't thought of." |
