EDA vendors ponder 90-nm tools
By Richard Goering and Michael Santarini
EE Times
(08/16/02 04:35 p.m. EST)
SAN JOSE, Calif. — Major EDA vendors are preparing a clear message for chip designers: The 90-nanometer process node requires considerable retooling. But there are questions about how much of a change the 90-nm generation really represents and when designers will embrace it, given that relatively few developers have even made the transition to 0.13-micron designs or tooling.
There's an acknowledgement that 90 nm doesn't so much create new problems as exacerbate existing ones. "Issues emerge over time in a creeping fashion," said Tom Ferry, vice president of marketing and IC implementation at Synopsys Inc. "You start to see things at 130 nm that become major at 90 nm and become killers at 65 nm."
Cadence Design Systems expects to release a 90-nm road map in September and has written a white paper on 90-nm design challenges.
Synopsys is "not looking at any particular date" for a 90-nm announcement, Ferry said, but it is already working with foundries on new design rules and more accurate models.
Gary Smith, chief EDA analyst at Gartner Dataquest, doesn't think 90 nm is that big a deal. The methodology and tool flow for 90 nm have already been worked out and have been proved by the power users who adopted 0.13-micron design tools and flows two years ago, he said.
"If you talk to a power user about the problems at 90 nm, he will yawn and say 'Go away; we're working on 70 nm, where we really have problems,'" said Smith. But he added that designers who skipped the 0.13-micron node and are looking to implement designs in 90-nm processes are finding they have to license new tool flows to complete designs.
Given the relaxed pace of the 0.13-micron transition, there's also the question of when 90 nm will truly become a force to reckon with. Ping Chao, senior vice president and general manager for digital IC solutions at Cadence Design Systems, said the company is "working with design teams doing 90 nm today. We see early tapeouts happening next year, with production in two years or so."
Bryan Lewis, silicon analyst at Gartner Dataquest, acknowledged some slowing in the adoption of 0.13 micron due to the downturn but said power users are still moving to ASIC vendors' latest processes.
"It sounds like the tool guys are again saying, 'You have to have this stuff,' " Lewis said. "It may ring somewhat true from the design side, but I haven't heard anyone from the silicon side say there are any show-stopper roadblocks at 90 nm."
Preliminary usage figures from Lewis for 2002 show that 22 percent of roughly 6,500 design starts will have occurred at 0.13 micron, up from 7 percent in 2001. But, said Lewis, 43 percent of design starts, representing the mainstream, will have been at 0.18 micron, and a similar number at 0.25 micron.
Lewis has not yet made predictions for next year's process adoption rate, admitting that it will likely be complicated by the slowing economy.
Down to the wire
From Cadence's standpoint, 90 nm is all about wiring delays. Cadence's white paper states that by the 90-nm node, wiring or interconnect delays will account for 75 percent of total delay. What's really new, said Chao, is the impact of signal integrity on that delay. "No longer can you just estimate wire length," he said. "You've got to look at coupling to neighboring wires, and at wire width."
IR drop emerges as a major impact on delays as well. According to the Cadence paper, an IR drop from 1.7 volts to 1.6 V can produce delay variations of 50 percent or more.
Further, Chao said, it's important to look at wiring across the entire chip. That leads to a methodology that Cadence calls "continuous convergence." It begins with a silicon virtual prototype (SVP) — a full-chip design representation, with wires. This prototype serves as a universal cockpit and treats all aspects of the design — logic, timing, power drop, signal integrity, electromigration and manufacturability — concurrently.
"Essentially we have the notion of a virtual tapeout every day," Chao said. That means, he said, that the SVP must be fast enough to allow a one-day turnaround on a new implementation.
But 90-nm designs will typically have 10 million gates or more, Chao said, forcing continuous convergence to support both hierarchical and flat designs. Because of the huge capacity requirements, Chao advocates the use of "dials." That might mean, for example, that a user would do an initial full-chip physical synthesis run at "medium effort" for fast results and then turn up the dial to "high effort" for a more accurate synthesis of a half-million-gate block.
Chao also said 90-nm routing must handle timing and signal integrity concurrently, a feature of the Nanoroute router that Cadence recently acquired from Plato Design Systems. Post-route parasitic extraction is still needed, however, and it needs to consider such issues as signal electromigration, power grid analysis and inductance.
But inductance won't be a critical concern until 65 nm, Chao suspects. Neither is he sure about the severity of yield-optimization and process-variation concerns at 90 nm. But it's important to start looking at those issues now, he said.
Synopsys' Ferry said his company views timing and signal-integrity "closure" as the primary 90-nm design issues. He added that 90 nm presents challenges in design complexity, "reliability signoff," routing support for design rules, parasitic extraction for new effects, design-for-manufacturability and power management.
And there are other issues. "Maybe in the past you did metal fills after GDSII and didn't incorporate that into the signoff loop, and maybe you have to now, because it has a discernable effect on timing," he said. "And metal polishing may have an effect on parasitics that you have to take into account."
A new concept, reliability signoff, will require designers to check electromigration (EM) and IR drop, Ferry said. "You may have to have a tool help split up nets and vias to meet EM rules," he said. Further, more design teams will have to work with such resolution-enhancement techniques as optical proximity correction (OPC). But Ferry was unsure to what extent 90-nm designers will have to worry about yield optimization.
For routers, the chief 90-nm issue is meeting design rules, such as those for metal fills or antennas, Ferry said. But he agreed with Chao that routers must have some signal-integrity awareness as they route, followed by more-accurate post-route extraction and analysis.
Ferry also said that power management becomes critical at 90 nm, because more designs will be low-power. And static leakage current becomes a daunting problem at 90 nm and below, he said.
Capacitance rules
Magma Design Automation is also eying how crosstalk and IR drop affect delays at 90 nm. "The variation of capacitance properties across the chip seems to be much greater at 90 nm than at 0.13 micron," said Rajit Chandra, vice president of technology at Magma. "If you want to do timing closure, you have to account for the variations just to ensure you don't have a violation."
Chandra said that Magma's customers today are looking at how timing is affected by crosstalk and are asking for IR drop solutions at 0.13 micron and below. Magma is updating its tools to look concurrently at timing, crosstalk and IR drop, he added.
Power becomes a first-order effect at 90 nm, so "everyone needs to design for low power," Chandra said. And libraries will need to be characterized to deal with noise effects and power effects. That will require the use of the Advanced Library Format (ALF) format or perhaps an expanded version of .lib.
Inductance will still be manageable at 90 nm, but that could change at 70 nm and below, Chandra said. He said Magma doesn't expect to see manufacturability issues enter the flow until 70 nm hits the market.
Dave Reed, vice president of marketing at Monterey Design, said one big difference at 90 nm is the way signal integrity will be handled. At 0.13 micron, he said, people have been able to repair signal integrity problems after routing. "At 90 nm, we think people won't have a good experience doing the post-place-and-route repair step," he said. "It will need to be done during the design process with prevention tools."
Power will also be problematic, Reed said, since almost half of the power consumption on a 90-nm chip will be due to leakage power.
Reed noted that there will be new design rules to support at 90 nm, including special spacing for via arrays, new via-stacking rules, and length-dependent notch rules. On-die process, power-supply-drop and temperature variations will become significant.
Joe Sawicki, general manager of the PVX Division at Mentor Graphics, said there are indeed significant challenges in the areas of mixed-signal integration, signal integrity and back-end processing, including resolution enhancement technology (RET). But the real crunch point for manufacturability tools will occur at 65 nm, Sawicki believes.
"The realities of scanner delivery mean that implementing [the 65-nm] node will require a new class of RET on the design data called strong techniques," said Sawicki. "There are a number of different options here, but all of them will have an impact on the shapes the designer can use to implement a design and the NRE cost for the mask.
"It is critical to work through these challenges in order to ensure the delivery of this node." |
