To: Ilaine who wrote (38540 ) 8/20/2002 5:51:35 PM From: Bilow Respond to of 281500 Hi CobaltBlue; Re US actions that will decrease efficiency of foreign competitors, as well as US Dept. of Defense efficiency. One of the jokes in the engineering community is that the US Deptartment of Defense created the VHDL language in order to devastate Europe's integrated circuit development. Here's a link:The Popularity of Verilog HDL Why most designers in the US, Japan and Asia use Verilog HDL as their high level design language. ...VHDL -- Language by Committee VHDL was developed by committee and intended for documenting digital hardware behaviorally. The DOD’s specification for the language was solely for the explicit purpose of documentation. It originated out of the VHSIC (Very High Speed Integrated Circuit) Program as a part of a US DOD (Department of Defense) project in 1981 . When completed in 1985, it was called VHDL 7.2. ... Today the only geographic location where Verilog HDL does not have overwhelming dominance is Europe. ... There is a real danger of Europe becoming the Third World of tomorrow.” [Steven Poole, European Manager, Intel Corp., Time, 14 October 1996] ... DOD has mandated the use of VHDL (for documentation) for all electronics work contracted by the DOD, the use of Verilog HDL falls outside of this mandate. But, reality notwithstanding, the DOD and its contractors must deliver on their contracts in a predictable and expected timeframe. To meet these goals, in addition to some of the new cost containment objectives, the use of Verilog HDL has become necessary by default. One government branch which has been deploying Verilog HDL for their mission critical designs is the National Security Agency (NSA). By using Verilog HDL, their design teams have been able to dramatically reduce the time to develop new technologies. This keeps them ahead of the curve for the sensitive communication electronics which they design, develop and deploy. NSA has elected to meet its design objectives and budgets rather than be subjected to the delays and cost overruns associated with using VHDL. ...parmita.com -- Carl