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To: Dan3 who wrote (169620)8/20/2002 12:18:04 AM
From: Tenchusatsu  Respond to of 186894
 
Dan, that's why AMD is going with a larger cache for Barton. When your processor runs ten times faster than the bus, you might want to reduce the amount of FSB traffic.

That's also why AMD wants an integrated memory controller. When you have to go out to memory, every saved bus clock in latency counts.

"Gotta get to Hammer ..."

Tenchusatsu


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