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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (87561)	8/23/2002 9:18:30 PM
From: brushwud	Read Replies (1) \| Respond to of 275872

I am curious about this constant padding by hardware. Suppose you have a statement that says load 1 to register, say A. Your code can say that, but when the assembler generates executable code, it has to represent the number 1 as something, I mean a value stored in executable with some width. Doesn't the width have to be the size of the register you are loading? On x86, you can operate on signed 8-bit immediate (or literal) data and produce an 8-, 16-, or 32-bit result. Or you can use 16- or 32-bit immediates. On x86-64, you can also produce 64-bit results. I seem to recall that 386 has special instructions to load only low portion of a register. So if this instruction is used, you have loaded the low portion of the register, say only 8 or 16 bit representation of number one, but what happens to the high part of the register, especially if you want to use the number if full 32 or 64 bit operations? On x86 or x86-64, 8- or 16-bit operations only modify that much of a register, but on x86-64, 32-bit results are zero-extended into a 64-bit register.

To: Joe NYC who wrote (87561)	8/23/2002 11:18:18 PM
From: TechieGuy-alt	Respond to of 275872

I seem to recall that 386 has special instructions to load only low portion of a register Actually, there is no such thing as a monolithic register (at least in x86). Each x386(and higher) registers can be addressed as (using the accumulator as an example): AL(lowest 8 bits), AH (next 8 bits), AX, the entire 32 bits and now RAX- all 64 bits in x86-64. There are explicit instructions that address only the register portions that you want. If you address a smaller portion of a larger register, the unaddresses contents (usually) remain unchanged. At the assembler level this is done by explicit nemonics. At the opcode level it is done either explicitely (depending on the current mode of operation (16 bit, 32 bit (and now 64 bit) etc. or by override prefix bytes that change the default register, or data sizes- telling the uP the data size involved. I believe this is how AMD is managing to extend x86 6o 64 bits and keeping it backward compatible with x386. They have introduced a new mode for 64 bit as well as a new operand prefix to load 64 bit registers (amount other things). TG