Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Road Walker who wrote (170096)	8/26/2002 12:21:43 PM
From: wanna_bmw	Respond to of 186894

John, Re: "Yield and reliability issues threaten the touted dual-damascene copper interconnect structures of leading 130-nanometer processes, having caused both poor yields at wafer sort and unacceptable failure rates over the life of apparently good chips, according to a wide range of industry sources." Looks like Yousef, Elmer, and others have been right all along. Intel's .13u process is far beyond the rest of the industry, who continues to face problems in trying to keep up. I wonder if AMD has been exposed to any of these problems, or if some of these issues are responsible for their lower yields (since they've been using dual-damascene copper interconnect since .18u). It sounds like the foundries are particularly susceptible (TSMC was mentioned in the article). This doesn't sound too good for AMD's upcoming partnership with UMC, but I guess that argument has already been argued fairly thoroughly here. wbmw