To: Ali Chen who wrote (170449 ) 8/31/2002 4:33:12 PM From: Dan3 Respond to of 186894 Re: A single processor executes threads sequentially, therefore there will be no additional benefits for 1P Athlon, only extra time-sharing overhead. But that's the whole point of multi-threading CPU cores - if there are execution units standing idle because one thread can't keep them filled, pull instructions from another thread and dispatch those to the available pipeline units. You will need another instruction counter, but I would imagine Intel's hyperthreading does that already, it would defeat the purpose of hyperthreading to have to push the PC's value onto a stack and pop the value for the other thread's PC before moving on, I'm sure they just switch PC's. There are some circumstances in which more execution units are needed even for a single thread. One thing that's easy to forget is that X86 instructions are CISC instructions, which are then decoded into multiple micro-ops, so that one instruction per clock can result in multiple micro-ops looking to be dispatched, per thread, per clock. Some discussion of concurrent CPU operations that take place for single CISC instructions is in Hans de Vries' famous article found here: chip-architect.com And I was also speculating (which I should have made more clear) that Athlon has sufficient resources available to it such that it might be able intermittently run multiple threads concurrently, as though it were two complete cores, and not just switch between threads when the pipelines stall. I suppose that will partly depend on how many rename registers are available to it - but since Athlon has 88 registers available to be renamed as the 8 classic X86 registers, I would think that it would do well supporting concurrent threads, or even processes, with the addition of only a few control structures. Regards, Dan