300-mm transition looks tougher for foundries
By Mike Clendenin
EE Times
(09/20/02 10:46 a.m. EST)
If the 300-mm wafer transition had a slogan, it'd be this: It's not the technology, it's the economy, stupid.
Whether referring to the global economy or economies of scale, the e-word is making or breaking IC companies' early efforts to fabricate chips on 300-mm wafers.
Among the pioneers, Intel Corp., Infineon Technologies AG and ProMOS Technologies Inc. are comfortably progressing with the transition. IBM Corp., Motorola Inc. and Samsung Electronics Co. Ltd. are joining them. But question marks hang over other would-be leaders, most notably the foundries.
Last week, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) halved its capacity target for state-of-the-art 300-mm wafers to 5,000 per month by this December — about where it is now. United Microelectronics Corp. may do the same, but at the moment UMC is sticking to its goal of 10,000 wafers per month this year.
Taiwanese memory maker ProMOS said last week that it expects its 300-mm (12-inch) wafer fab to achieve its maximum capacity, of 9,000 wafers per month, by December, despite the problems inherent in such a transition. Intel is already running the Pentium 4 microprocessor on a 130-nanometer process using 300-mm wafers and is doing pilot work on 90 nm.
Also last week, Samsung Electronics said it expects to graduate from 300-mm pilot lines to mass-production during the second half of 2003, using a 90-nm process to make high-density, 2-Gbit NAND flash and other products slated for high-volume runs.
The theme appears to be that integrated-device manufacturers (IDMs), which run fewer products than foundries, are having a much easier time with the ramp-up.
"In our experience, we have brought up the 12-inch fab in almost the same time frame as the 8-inch," said Len Mei, vice president of manufacturing at ProMOS.
"Our yield from the 12-inch is almost equivalent to the yield from the 8-inch during the same time frame," he said. "The only reason people don't want to build more 12-inch fabs now is the business consideration, not the technology consideration."
Endless upgrades
ProMOS was one of the early movers on 300 mm. With the help of its partner, Infineon, the DRAM company set up its equipment early last year, qualified first products in March of this year and then started to ramp 0.14-micron technology in April to make 256-Mbit DRAMs. By the end of the year, ProMOS expects to reach full capacity on the first stage. Using the larger wafers will yield about a 30 percent savings per die — an undeniable asset in the cutthroat commodity-memory business.
But the transition has been far from trouble-free. "It's a headache for engineering. There are many bugs in the software that create many issues," said Rebecca Tang, director of the manufacturing engineering division at ProMOS.
Standards from Semiconductor Equipment and Materials International (SEMI) "only provide guidelines for tool vendors," she said. "We have experienced endless hardware and software upgrades [in recent months], and this applies to all the tools — no exceptions."
As many problems as ProMOS has had, it didn't have to deal with new materials, such as copper interfaces and low-k dielectrics, Tang noted. But the foundries do.
Harder for foundries?
Indeed, engineers are facing a laundry list of problems as they simultaneously tackle larger wafers and smaller geometries. "If you choose to develop [your 130-nm process] on 200 mm, then the pain will be in porting the technology to 300 mm," said Eric Hsiung, a senior manager in UMC's R&D division. "But if you develop the technology on 300 mm, then you will have specific problems associated with 300 mm."
Defect characterization is becoming ever more important — and more difficult. More-sensitive (and more-expensive) defect detectors are being used for the most insidious die killers; but using an e-beam system, for instance, will substantially reduce throughput.
"For a 300-mm wafer, a 0.1-micron defect is equivalent to a person in the continental United States. It's that kind of ratio," Mei said. "Just imagine: On a 300-mm wafer, if you want to catch a 0.1-micron defect, the area you have to scan is equivalent to flying your jet across the United States, from north to south and east to west. That's why e-beam, which is very sensitive, takes so long. Ten hours a wafer is already pretty fast."
Sometimes, the bigger problem is achieving the volumes at 300 mm to justify the shift to a 130- or 90-nm process. Spinning designs on 130 nm raises the stakes to a level that is already making many designers uncomfortable at 200 mm.
At 130 nm, masks cost about $600 million a set. At 90 nm, that figure will balloon to between $1 million and $1.5 million, depending on the number of metal layers.
"My friends working on circuit design said they are very nervous taping out," said Chiang Shang-yi, senior vice president of 300-mm R&D at TSMC. "We all make stupid mistakes. In the past, when mask costs were $100,000 and they made a stupid mistake, their boss usually let them get by. But when a mask set costs $1.5 million, a stupid mistake could cost them their jobs."
Among the foundries that have entered the footrace to 300 mm, UMC may have the edge. Its early work with Hitachi Ltd. as a partner in Trecenti Technologies, a 300-mm fab in Japan, gave the foundry first-mover experience. Plus, since big-die devices like CPUs have the most to gain from 300-mm wafers, UMC will be able to use its recent partnership with Advanced Micro Devices Inc. to its advantage. AMD is supposed to farm out some of its Athlon production later this year to UMC as part of a growing manufacturing-and-development relationship. That would help UMC boost its 300-mm utilization and give AMD much-needed die savings — economies that rival Intel has already begun to reap.
For TSMC, however, the benefits of the big wafers remain elusive. Chiang conceded that the company may have moved too soon on 300 mm.
Tough call
As business conditions remain flat, more analysts are starting to wonder the same thing. It's a tough call, say industry insiders, because to remain leaders, both TSMC and UMC had little choice but to take the plunge. (Chartered Semiconductor Manufacturing Pte. Ltd., the world's third-largest foundry, said this past week that it would accelerate its transition to 300-mm wafers, and expects to have 300-mm lines in production by the third quarter of 2003.)
Yet the success of the first companies that master 300 mm will play out in enormous ways, predicted David Wang, executive vice president at Applied Materials Inc. Wang has tracked the fortunes of all semiconductor companies over the past 10 years. During the first five-year period, five companies took 70 percent of all semiconductor industry profit, he said. In the last five-year period, those same five companies claimed 90 percent. "What that means is that the industry [is] a winner-takes-all game," Wang said.
The largest negative impact, meanwhile, looks set to befall ASIC designers, who may only want to run 500 wafers over a product life cycle. "At 300 mm, that would be only 200 [wafers]," said Chiang. "If your mask costs are more than half a million dollars to produce only 200 wafers, that's very expensive."
Bill Arnold, chief scientist of ASM Lithography Holding NV, suggested the industry up the ante for other front-end approaches. "For the very low-volume business segments, where the mask cost dominates, there may be a role for so-called maskless lithography. That's a topic of interest to many of the lithography companies today," he said.
Initially, 300 mm was talked about for the 250-nm process transition and then again for 180 nm. While 130 nm looks to be the turning point for Intel and a few others, the foundries may be forced to wait longer.
"If you have a one-product system like Intel, that's optimum. That doesn't work in a foundry, where you don't know where your products are coming from. They are taking in designs from 250 independent guys plus the IDMs, so it's a much more difficult problem for TSMC and UMC than it is for Intel," said Cary Halsted, vice president of field operations for KLA-Tencor Corp.
There is another variable that is proving itself influential. Over the past decade, with the pressures heaped on process migrations, fewer bugs are being worked out before a new technology node is introduced. So initial yields are lower, and many of the integration issues, which historically may have been handled as a part of the integration phase, are pushed off to the manufacturing phase, said Kimon Michaels, vice president of integration practice at PDF Solutions Inc.
Consequently, the time to stable, high-volume production is not just time-to-tapeout, as designers once expected. If designers have not taken into account the special needs of advanced nodes, such as redundant vias, then there may still be many hurdles to reaching mass volumes.
Little time
Meanwhile, even as the process-design integration issues worsen, the industry is shifting from a PC-driven focus to a consumer-driven business, with an attendant shrink in the time to high-unit-volume sales. "Even with something like the cordless phone, the time required to ship a million units can be measured in years. With Playstation 2, during the initial release, they shipped a million units in a three-day weekend," Michaels said. That has an impact on the process-design interaction. First, time-to-volume-production shrinks, despite all the pressures of today's parallel technology transitions. "The ability to solve process-design interaction in the fab over a long period of time, taking a fairly empirical approach, is gone," Michaels said.
As the influence of the consumer segment grows, the sensitivity of shopping seasons will make timing issues even more critical, he said. "You can't move Christmas. If you are late by a month, it can have a dramatic impact on your total sales for the whole year."
Michaels cited Microsoft Corp.'s Xbox gaming console as an example. Last year's game wars were marked by ordnance problems — limited supplies of units available for shipping during the holiday season. In part, the shortage could be traced back to Nvidia Corp., which sells graphics processors into the Xbox. The chips are made at TSMC, which was under pressure at the time to overcome problems on the advanced technology nodes used to make the Nvidia chips.
"Do I think the foundries are OK with 12 inch? I don't know yet," said Arthur Zafiropoulo, chief executive officer of Ultratech Stepper Inc. and this year's SEMI chairman. "I think there is more risk there because they don't have the volume on one set of masks."
But if the foundries can make an early go of it at 300 mm, Zafiropoulo said, TSMC chairman Morris Chang is the one who can shepherd it through, just as Gordon Moore saw Intel through its tough transitions, such as the move to 150-mm wafers.
Intel was "just burning cash like crazy," Zafiropoulo said, and Moore "was asked by the press about what was happening in Albuquerque [N.M.] with the 6-inch wafer line. He said, 'We're eating like an elephant and defecating like a canary.' That was a super description. Moore's a smart guy. So is Chang. He made the foundry happen. So who am I to say the chairman of TSMC is wrong to go into 12-inch wafers?" |
