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Technology Stocks : Xilinx (XLNX) -- Ignore unavailable to you. Want to Upgrade?

To: SemiBull who wrote (2883)	11/13/2002 7:50:22 PM
From: SemiBull	Respond to of 3291

300mm volume drive for Xilinx By Chris Edwards EE Times (11/12/02 10:42 a.m. EST) MUNICH — More than 30 percent of the FPGA supplier Xilinx's production is now coming from 300mm fab lines as yields come up to match those on older 200mm lines and, in one case, surpassed the yield seen on 200mm, its chief executive said in an interview. The company expects half of its production, measured by total die area, to have moved to 300mm by the end of the company's current financial year. Wim Roelandts, president and chief executive, told EE Times here at the Electronica trade show that at the moment, all of the 300mm production is at UMC, which supplies 70% of the company's overall chip demand. But Xilinx has taped out a design aimed at IBM's 300mm process currently undergoing tests. Roelandts said the 300mm production is currently on the 150nm node and on a hybrid 150/180nm process. The IBM line will bring 130nm parts using both copper metallization and a spin-on low-k dielectric onto 300mm production lines. “130nm will have to be done on 300mm because that is what the most up-to-date equipment is designed for. The people who say they can stay with 8in [200mm] will find that out,” said Roelandts. “If you want to do 130nm with good yields, you have to do it on 300mm. On the hybrid [150/180nm] technology, the yield is now better [than 200mm]. For pure 150nm, it is at parity and continues to improve. Over the long term, it will be better.” Bigger wafer, better yield Part of the potential yield improvements come from the larger wafer, said Roelandts. “Defects come in from the side.” But the main potential boost to yields comes from the equipment: “It is more modern, almost peopleless, and is producing better results.” Roelandts said he expects the high-end device production to come mainly from IBM as the company has been able to combine a spin-on dielectric, which typically has a lower dielectric coefficient (k) than the materials used by most other foundries on 130nm, with copper metallization. “130nm has been a lot more difficult than people expected, but it is not slowing down deployment of 90nm,” said Roelandts. Problems with low-k dielectrics, particularly spin-on materials has convinced many foundries, such as UMC, to step back to more conventional dielectrics that can be placed on-chip using chemical vapour deposition (CVD). UMC will produce 130nm devices, but using one of the CVD dielectrics. “IBM is the only who keeps pushing ahead with low-k. The good news is we are working with IBM. You lose 10 to 15% performance without low-k,” said Roelandts. “We are still planning to use UMC for more low-end products: we will be keeping both fabs occupied. UMC hasn't given up on low-k. They realise that, for the future, they have to have it.”