Toshiba takes lead in 90-nm race with SoC process
By Mark LaPedus
Semiconductor Business News
(01/13/03 01:49 p.m. EST)
SAN JOSE--Hoping to get a jump on its competitors, Japan's Toshiba Corp. here today disclosed it has begun sampling its 90-nm (0.09-micron), system-on-a-chip (SoC) technology, with "volume production" slated by the second quarter of 2003.
In the 90-nm process technology race, Toshiba appears to be running slightly ahead of its competitors, according to analysts. IBM, Intel, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), and others are also separately developing 90-nm technologies, with plans to offer the process in volumes later this year, according to analysts.
Toshiba's new SoC technology, dubbed TC300, is built around the company's CMOS process--CMOS4. This process was jointly developed by Toshiba and Sony Corp. of Japan. The two companies are also working on 65-nm CMOS process technology for embedded DRAMs (see Dec. 2, 2002 story ).
Toshiba's 90-nm, SoC technology is an 11-layer process, equipped with copper interconnects, low-k dielectrics, and other features. The CMOS4 process enables mixed signal ICs, embedded DRAM, and application-specific intellectual property (IP) on the same chip. Supporting logic densities up to 400,000 gates/mm2, the TC300 process is targeted at next-generation, high-end applications, such as consumer, computing, and networking.
TC300 delivers roughly a 100% increase in gate integration, a 20% increase in gate speed, and a 50% reduction in power consumption, compared to the company's 0.13-micron process technology, according to Toshiba's U.S. chip arm, Toshiba America Electronic Components Inc. (TAEC).
Unlike its competitors, Toshiba implemented a low-risk, 0.13-micron production strategy, by deploying an aluminum-interconnect version into production first, and following with a copper-interconnect version, said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC in San Jose.
"As a result of our high-yield, high-volume approach, our 0.13-micron SOCs have been in production since October 2001, and we are currently shipping high-volume production quantities,” he said in a statement. “Having already shipped our first TC300 customer samples, we are on course with our new 90-nm technology."
The TC300 process offers input/output (I/O) cells, such as serializer/deserializer (SerDes) chip-to-chip interface applications, as well as Gigabit Ethernet, Fibre Channel, Sonet, and Wi-Fi.
The embedded DRAM process employs Toshiba's trench capacitor technology, which permits a mix of logic and DRAM processes without degrading performance.
Two kinds of DRAM cores are available-SD and FA. The SD-type DRAM has a clock cycle of 300-MHz maximum and a data transfer rate of 9.6-gigabytes-per second (GPS) maximum. The FA-type DRAM is optimized for fast access with a random access time range of 6-8 nanoseconds and an I/O width of 288 bits maximum.
A range of package types for high-performance SOCs are available, including 200-2,304 FCBGA, 109-256 PFBGA chip-scale packages and a 256-868 pin PBGA packages.
TC300 is now available for immediate design acceptance and the first customer samples have already been shipped. TC300 is slated to begin ramping for mass production in the second quarter of 2003 with high-volume production expected in the third quarter of 2003. |
