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Technology Stocks : ARM Holdings (Advanced RISC Machines) plc. -- Ignore unavailable to you. Want to Upgrade?

To: Bruce Byall who wrote (683)	3/3/2003 11:04:54 AM
From: Bruce Byall	Read Replies (1) \| Respond to of 912

ARM and Synopsys Announce Availability of Reference Methodology for All Synthesisable ARM Cores Monday March 3, 5:01 am ET CAMBRIDGE, England & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--March 3, 2003--ARM ((LSE:ARM - News); (Nasdaq:ARMHY - News)) * Streamlined Process Speeds Deployment Time and Increases Quality of ARM Core Implementation ARM, the industry's leading provider of 16/32-bit embedded RISC processor solutions, and Synopsys, Inc. (Nasdaq:SNPS - News), the world leader in integrated circuit (IC) design software, today announced the availability of the ARM-Synopsys Reference Methodology as an integral part of all ARM® synthesisable cores. The ARM-Synopsys Reference Methodology significantly streamlines the process used by ARM Partners to port synthesisable ARM microprocessor cores to their chosen technologies, by reducing the time required to harden and model the core from months to weeks. The new ARM11(TM) core family, announced at the end of 2002, was the first synthesisable ARM core to be released with the ARM-Synopsys Reference Methodology fully integrated into the product. All ARM synthesisable core families-- the ARM7(TM) family, the ARM9E(TM) family, the ARM10E(TM) family and the ARM11 family -- have now been upgraded to include the ARM-Synopsys Reference Methodology as an integral part of the product. "Providing a superior reference design flow is strategic to our business," said Simon Segars, excective vice president, engineering at ARM. "When we enable ARM partners to do their own physical implementation starting from synthesisable ARM cores, we must provide proven methods for retaining compliance with our architecture in their implementation process. Our ongoing collaboration with Synopsys is enabling us to maintain our target of ARM core use being as easy as deploying a compiled RAM cell, thereby giving our partners a significant market advantage." The ARM-Synopsys Reference Methodology provides an efficient, proven route from the register transfer level (RTL) to GDSII, creating a core that is compliant with the ARM architecture, and which has the necessary models required to deploy it as a reusable component. This "application specific" hardening enables ARM partners to benefit from the flexibility of a soft core while maintaining the predictability, performance and ease of deployment of a hard core. "The ARM-Synopsys Reference Methodology takes full advantage of Synopsys' complete RTL-to-GDSII tool flow including, the new SoC test automation solution in Synopsys' DFT Compiler SoCBIST," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "The key components of the ARM-Synopsys Reference Methodology -- Design Compiler, Physical Compiler, Astro, and PrimeTime -- are also the anchors of our recently announced Galaxy(TM) Design Platform. We will continue working with mutual customers to accelerate their deployment of ARM's synthesisable cores." Availability The ARM-Synopsys Reference Methodology is available now from ARM, as an integral part of the latest release of each synthesisable core and supports the following Synopsys tools: Floorplan Compiler, HDL Compiler(TM), DFT Compiler(TM) SoCBIST, Physical Compiler®, DC Ultra(TM), Power Compiler(TM), Design Compiler®, PrimeTime®, DesignWare®, TetraMAX®, Formality®, VCS(TM) and Astro(TM). The Reference Methodology is modular and based on standard interfaces allowing for the integration of complementary tools.