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To: SemiBull who wrote (25581)	3/24/2003 7:44:35 PM
From: SemiBull	Read Replies (1) \| Respond to of 25814

LSI ready with flip-chip packaging on low-k By David Lammers, EE Times March 24, 2003 (11:35 a.m. EST) URL: eetimes.com AUSTIN, Texas — LSI Logic Corp. said it is production-ready with flip-chip packages on an 0.11-micron process that includes low-k dielectrics. The soft, porous nature of low-k materials presents a challenge to packaging engineers, who must be careful that the stresses placed on the die within the package do not cause delamination within the interconnect. The stresses are particularly acute at the corners of the die, said Stan Mihelcic, senior manager of advanced packaging solutions at LSI Logic. LSI gained experience at the 0.18-micron generation when it adopted a low-k material from Tricon Ltd., a U.K.-based supplier of CVD low-k materials and equipment. At the 0.11-micron node, LSI formed a process co-development partnership with Taiwan Semiconductor Manufacturing Corp. (TSMC) and switched to the Black Diamond CVD dielectric. Rani Vasishta, vice president of technical marketing at LSI, said much of the attention on difficulties with low-k materials has been on via poisoning, with relatively little emphasis on the packaging issues. "Most people in the industry still underestimate the challenges of doing flip-chip packaging with these low-k materials. We were able to get a head start on the issues because we adopted low-k at the 0.18-micron generation," Vasishta said. The stresses between the die and the package come from the different rates of expansion of the materials during thermal cycling. "The key enabler is the underfill material, an epoxy that is between the silicon die and the substrate. The underfill relieves the stress and prevents die cracking and damage to the low-k material on the silicon," he said. LSI maintains a large packaging engineering group, headed by Maniam Alagaratnam, an LSI vice president. Last year, LSI announced it had figured out how to extend wire-bond packaging to three-deep rows, increasing the number of interconnects to 1,096. That technology, called Pad on I/O, is optimized for low-cost consumer applications. Nevertheless, wire bonds are about 4 millimeters in length, and have "tremendous parasitics" compared with flip-chip packages, where the bumps on the underside of the die are about 90 microns in diameter, Mihelcic said. "Consumer products flourish in wire-bonded packages. But for products that have several megabytes of memory and need high bandwidth, flip chip is the way to go," Mihelcic said. LSI offers three different plastic (organic) flip chip ball grid array packages, starting with the FPBGA-4L (flip-chip plastic ball grid array — four layer), a low-cost substrate with the solder bumps on the periphery of the die. The bump pitch of 8 mils supports a total signal count of 1,016 I/Os. An intermediate package uses a six-layer organic substrate with two dedicated signal layers for an I/O density of 1024. The high-end package supports signal I/O placement in the core region of the die. Because the I/O slots can be placed towards the center of the die, smaller die sizes are possible with as many as 1,750 I/O signals, Mihelcic said. The announcement has implications beyond LSI Logic, as it has licensed its packaging technologies to several of the largest contract packaging companies worldwide. Among those licensees are Advanced Semiconductor Engineering, Inc. (ASE, Kaohsiung, Taiwan), the packaging and test company closely affiliated with TSMC. LSI Logic has worked closely with TSMC to launch the 0.11-micron process, and TSMC also uses the "Black Diamond" low-k dielectric, said Vasishta. With LSI Logic (Milpitas, Calif.) and TSMC (Hsinchu, Taiwan) using a very similar interconnect process, it is likely that TSMC and ASE would quickly be able to offer organic flip-chip packages at similar design rules to the fabless semiconductor companies served by TSMC and ASE, Vasishta acknowledged.