Lizze, some research on Ezchip. I just placed an order for
1000 more LNOP at 6.25.
analogZONE Says . . .
I guess I owe Eli Fruchter, EZchip's CEO, an apology. Although I was quite skeptical about his small band of battle-hardened siliconistias plans to deliver its highly ambitious NP-1 processor, a multi-stage, multi-CPU, programmable pipelined packet processor, the chip has been shipping since April. And despite the six-month delay in its arrival (which I did correctly predict), the NP-1 seems to be a pretty solid product that has garnered several significant sales, including a couple of name-brand players. The sales seem to have put the company into an enviable position, making it one of the few chip makers in the Valley to actually grow headcount (60 to 90 people) in the past year. So, based on Ezchip's past performance, I'll cut them some slack with the release of their NP-1c, an improved version of the NP-1shipping in Q1 2003.
The NP-1c uses the migration from the NP-1's 0.18 micron CMOS process to IBM's 0.11 micron (more like most company's 0.13 process) fab line to add performance and features, while dramatically slashing prices by 30%. This in effect throws down the gauntlet to competing NPs, and to the traditional ASICs that compete with NPs to meet a new price-performance benchmark.
EZchip's '1c shares much of the architecture and almost all of the instruction set of its predecessor. The guts of the machine still consist of four multi-processor stages that perform (in sequence) inspection and parsing based on header (and some content), searching for route addresses, address resolution, and packet modification. It also contains the gobs and gobs of on-chip memory, plus some very clever search tree logic that allows all buffering and lookup functions to be done using a couple of inexpensive DRAMs instead of the SRAMs and CAMs used by most other chip sets.
The new chip on the block adds channelization, an important feature for making efficient use of the existing SONET infrastructure that comprises the bulk of our metro access and long-haul networks. Using an external channelized framer from PMC-Sierra, the NP-1c can support 16 ports of OC-12 traffic, four ports of OC-48, and one OC-192 port. I think Fruchter and crew made a wise choice here since there will be lots of OC-48 and even OC-12 ports out there at the edge for quite some time to come. Another important upgrade to the NP-1 is its ability to provide time-shared interface to multiple low-speed ports via its SPI-4.2 interface, as well as the earlier XGMII / GMII / RGMII / TBI port interfaces. I applaud the choice to support SPI-4.2, since it is a very nice LVDS-based high-speed port technology that is on its way to becoming a standard for several different applications.
With the popularity of SPI-4.2, it's no wonder then that the NP1c also supports the SPI-4.2 version of the NPF's CSIX switch fabric interface. After a couple of years of struggling, the CSIX spec (under the wing of the NPF) is beginning to catch on and pay off on its promise. For one thing, the standard interface has allowed EZchip to partner with Broadcom, IBM, and ZettaComm, for switch fabric and PMC & Broadcom for PHY interfaces in reference designs.
The bottom line of their move to the 0.11 micron process is that they expect the shrink to double the processing power (through increased clock speed and more processors in each of the chip's functional blocks), plus a 30% cost reduction (we'll get to this in a minute.)
I'm reasonably confident in EZ Chip's claims that the '1C will provide sufficient processing punch and classification memory for many applications. Like the original NP-1, it uses a wide, fast internal DRAM (plus proprietary hash and tree algorithms) for classification and only results are stored externally with 1-2 accesses required per operation. This combination of speed and capacity lets the chip search through up to around 2 M table entries at OC-192wire speeds.
The above-mentioned DRAM interface can address up to 2 Gbyte of external memory, leaving considerable room for future requirements (a typical large route table requires 300 Mbytes today.) This is important for IPv6 apps which have huge route tables (four times IPv4), and a necessity in Far East where IPv6 is now the protocol of choice because of the huge numbers of ports coming on line every day.
With the NP-1 doing so well in the field, I only have a few concerns about some of the claims made for the NP-1c. It seems to me that the chip's fully-programmable architecture is at once its strength, and its potential point of vulnerability. The flexibility it affords lets it be used to provide specific services (VPNs, firewalls NAT) or other tasks at the blade, and can be reprogrammed as needed. On the other hand, I worry that even with the highly-optimized architectures used for each of the four blocks, they will not provide as much performance as fixed-function logic in really complex operations. I am also a little concerned about the fact that the four arrays of highly-specialized processors would prove a programming nightmare in situations where it became necessary to bypass EZchip's compiler and hand-code critical software elements. EZchip assures me that their current development software makes it possible to program each section as a single very conventional processor in a high level language - even for critical loops. They also say that the programmer's job have become even easier since they put their new development systems in people's hands 6 month ago. With customers' prototype systems already up and running in the labs they expect to see NP-1-powered products becoming available in early '03.
And of course, the other compelling issue is price. Using some fairly reasonable assumptions, they claim up to an 80% reduction in cost and parts count over other NPs and ASICs through elimination of CAMS, SRAM , and other external components. Cost of a 10 G port can total $1500 to $10K, vs. an EZchip NP-1c and four DRAMS for about $820 - significantly less than many competing solutions. |
