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To: Rob S. who wrote (11494)6/11/2003 7:23:36 PM
From: SemiBull  Read Replies (1) | Respond to of 11555
 
IDT rolls out flow-control management ICs
By Robert Keenan, EE Times
Jun 9, 2003 (12:41 PM)
URL: commsdesign.com

WAYNE, N.J. — Two flow-control management device families from Integrated Device Technology Inc. combine logic, FIFO, SRAM and dual-port memory to handle such tasks as buffering, multiplexing/demultiplexing and domain transition in data path designs.

IDT hopes its approach will lighten the processing load normally carried by ASICs or FPGAs, thereby increasing packet-processing speed while reducing overall cost.

Designers traditionally perform jobs like buffering and mux/demux using a combination of on-chip logic and off-chip memory and FIFO components. With its QuadMux and MultiQueue devices, IDT has combined those functions into a single piece of silicon that can more effectively process packets and reduce gate counts in FPGA and ASIC designs, said Michael Olsen, director of strategic marketing at IDT (Santa Clara, Calif.).

Optimized for terabit routing and switch designs, the IDT72T552XX QuadMux family has three members: a 1-Mbit, a 2-Mbit and a 5-Mbit device. Each is equipped with