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Technology Stocks : Novellus -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (3470)	9/26/2003 3:29:16 PM
From: Proud_Infidel	Respond to of 3813

Executive Comment: Novellus' CTO on low-k issues If it doesn't lower capacitance, why bother? By Wilbert van den Hoek Silicon Strategies 09/26/2003, 2:00 PM ET The following contributed article was provided by Wilbert van den Hoek, chief technical officer and executive vice president of integration and advanced development and CMP Business Group for Novellus Systems Inc., a chip-equipment supplier in San Jose, Calif. The speed of a continually shrinking semiconductor device is no longer determined by the transistor, but by the performance of the interconnect. Over the last five years, the industry has had to choose between two key technologies--copper metallization and/or low-k dielectric films--to ensure continual improvement in device speed. The industry rapidly moved to copper metallization because it was the "easier" technology to implement. Today, after two generations of devices with copper, we are still facing the low-k intermetal dielectric (IMD) challenge. As semiconductor manufacturers look forward to the 65-nm process generation, they are being asked to choose between two different approaches to implementing low-k IMD films. One--the porous low-k approach--is a revolutionary, higher-risk strategy whose proponents promise the desired 20 percent reduction in capacitance commensurate with the associated risks. The other is a more evolutionary approach that fine-tunes both the low-k dielectric and copper metallization strategy to maximize the performance of the interconnect as a whole. The evolutionary approach promises smaller gains in capacitance reduction, but at a much lower risk. A review of the lessons learned from 130- and 90-nm low-k implementations demonstrates that the proponents of the revolutionary approach are focused on the wrong issue and, as a result, the rewards promised by their approach are actually illusionary. Rather than looking solely at the k value of the IMD film, our efforts should be targeted at the effective k value of the entire stack and the performance of the entire interconnect. At the 130-nm node, the industry needed to implement low-k to keep its 20 percent capacitance improvement expectations alive. Two primary low-k options emerged: spin-on films or plasma-enhanced chemical vapor deposited (PECVD) silicon oxycarbide films. At the 130-nm node, both these approaches failed, although not because of classic integration or unit process issues. Films could be deposited and interconnect stacks could be built. The failure was a result of film adhesion and mechanical strength issues that arose in the backend (i.e., packaging) of the process. As a result, the bulk of the 130-nm high-performance logic devices are manufactured today with fluorinated silicate glass (FSG). This 130-nm low-k implementation failure came from attempting to push the k-value of the IMD films as low as possible, without realizing the potential problems involved in integrating these inherently mechanically weak materials. The 2.7 low-k IMD film targeted for the 130-nm node had a hardness of approximately 1 GigaPascal (Gpa) for a PECVD film; significantly less for a spin-on. Such films lacked the mechanical strength needed to withstand the physical stresses involved in the packaging process. To avoid these pitfalls in the 90-nm node, semiconductor manufacturers have once again pushed back their low-k roadmaps and are implementing IMD films with significantly greater hardness (>2 Gpa), and as a result, higher k values of around 2.9-3.0. While these films have a higher k value than the 2.7 k films called for at the 130-nm node, companies implementing this lower risk, more evolutionary approach are seeing interconnect capacitance improvements that closely approach the 20 percent goal (relative to the k=3.6 FSG film of the 130-nm node). Despite these lessons, there are some in the industry still promoting the higher-risk, revolutionary approach as the only means to achieve a 20 percent improvement in capacitance at the 65-nm node. They correctly point out that using "dense" (k~2.7) IMD films with higher mechanical strength will only result in a 10 percent improvement in capacitance at 65 nm. They advocate the adoption of porous films (k<2.5) to drive down the k value of the IMD film. Unfortunately, such advocates are looking at the problem from the wrong perspective. They focus on the k value of the IMD film, instead of reducing interconnect capacitance, which is a function of the effective k value of the entire film stack. What they should be focusing on is tuning the metallization and IMD films as part of a holistic interconnect, rather than competing over whose IMD film has the lowest k value. While Novellus has demonstrated that we can deposit such porous films, the problem comes in integrating them into the stack. To build a viable stack, additional liner and cap films are required that result in an effective k value higher than that achieved with the lower risk evolutionary approach. In the end, we have added cost and complexity without addressing the fundamental problems associated with these mechanically weak materials. Prudent risk taking makes sense"-but only if it helps you achieve your goal. If an approach, no matter how elegant, technologically sophisticated, or bold doesn't achieve that goal, why bother--and especially if it is more costly. Clearly for the 65-nm node, the evolutionary approach makes more sense.