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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (7086)	9/8/2003 10:33:59 AM
From: Proud_Infidel	Read Replies (1) \| Respond to of 25522

The 65nm Chip Still Far Away Jessica Davis, Electronic News -- 9/5/2003 2:30:00 PM The 65nm chip remains a far away dream as companies continue to struggle to resolve the challenges of creating 90nm chips. The problem continues to become more evident with each design shrink beyond the 0.25 and 0.18-micron nodes: integrating the exotic materials necessary to make the design shrinks work. That was the consensus of a panel discussion of industry insiders in Menlo Park, Calif. Thursday, assembled by US Bancorp Piper Jaffray and Benchmark Strategies to discuss the challenges and opportunities of the 65nm node. Some of the more advanced chipmakers, equipment suppliers and R&D consortiums are just beginning R&D for the next node beyond 90nm. "We have not heard of any design starts at 65nm," said Jim Hogan, senior vice president of business development at IP company Artisan Components. "0.13-micron is just starting to become mainstream." The integration of a low k film continues to be a headache as well. At the 0.13-micron node, many companies that made the switch to copper opted for fluorinated silicon glass, rather than trying to overcome the problems of integrating next generation low k films with a k value less than 3. At 65nm, some companies are considering a hybrid approach of some sort among the various types of low k films and values, including possibly some sort of combination of spin-on polymer and organosilicate films. But in the near term, issues for integrating low k at 90nm have yet to be worked out for many. Doug Neugold, president of materials company ATMI, said he was aware of only one group that was successfully using low k dielectric film for 90nm. "The transition from 130nm to 90nm was not quite as had been hoped for," Neugold said. "There have been many challenges." Toshiba recently announced that it is using Applied Materials Black Diamond low k film and its BLOk barrier film in its 90nm production process for its TC300 family of ASICs. A major bottleneck for the 65nm will be the limitations of the standard silicon substrate, said Farhad Moghadam, VP and GM at equipment giant Applied Materials Inc. A potential solution may be ultra shallow junctions in the gates. Another may be seeking improved mobility through the use of other materials such as silicon germanium (SiGe). Many R&D engineers are looking at adopting a high k gate dielectric at the 65nm node, a next generation material beyond silicon oxide. The technical jury is still out on this material, although hafnium in some form or another as hafnium oxide or in combination with some other more standard material appears promising. Many researchers think the industry will have to adopt metal gates, however, in order to successfully implement high k gate dielectrics. In the meantime, there are other substrate alternatives between ultra shallow junctions and SiGe, such as using strained silicon, fully depleted silicon-on-insulator, and elevated source drains. But beyond the materials challenges, testing chips at the 65nm node may reveal unforeseen issues. The 65nm chips will likely see more failures due to cross talk and power issues, according to Barry Baril, CTO at ATE and design-for-test company Credence Systems. "Each generation creates new kinds of failures," he said. But there’s always room for innovation not yet envisioned that would make a 65nm chip possible. Perhaps design engineers will look at something entirely different to solve the problem, such as new transistor structures that could help shrink chips down to the next level, said John Kibarian, CEO of yield management software company PDF Solutions.