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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: Cary Salsberg who wrote (7211)	9/18/2003 11:01:36 AM
From: Proud_Infidel	Respond to of 25522

Singapore's Chartered enters 90-nm foundry race By Mark LaPedus Silicon Strategies 09/18/2003, 10:00 AM ET SINGAPORE -- Singapore's Chartered Semiconductor Manufacturing Pte. Ltd. today (Sept. 18, 2003) entered the 90-nm silicon foundry race, announcing a process technology for system-on-a-chip (SOC) and other complex designs. Chartered's process, dubbed NanoAccess, is identical to IBM's 90-nm process technology. Last year, IBM and Chartered announced a technology agreement under which the companies set plans to co-develop 90- and 65-nm process technologies. Chartered announced the immediate availability of its 90-nm design manual and Spice models to early adopters for design prototyping. Initial process qualification for both FSG and low-k dielectric options is targeted for completion by the first quarter of 2004. To further facilitate 90-nm design validation, Chartered is offering multi-project wafer (MPW) runs starting in October 2003. Chartered has qualified Japan's Dai Nippon Printing Co. Ltd. (DNP) for 90-nm photomask production. Another Japanese mask producer, Toppan Printing Co. Ltd., is currently under qualification. "We're announcing that Chartered is open for business at 90-nm," declared Chia Song Hwee, president and chief executive for Chartered, at a press event in San Jose on Wednesday (Sept. 17, 2003). Chartered's NanoAccess 90-nm manufacturing technologies are supported with third-party design libraries and tools, IP components, as well as design and manufacturing-related services. The technology features up to nine layers of copper metal, with options for full low-k and FSG. An optional triple gate oxide capability provides additional avenues for further optimizing power and performance. Transistor options include nominal, high performance (HP) and low power (LP) devices with input/output operating voltages of 3.3, 2.5, 1.8, 1.5 or 1.2 Volts. Core transistor operating voltages include 1.0 or 1.2 volts. Initial offerings include multiple threshold voltages in the nominal option. The LP transistor, which has a typical leakage (I-off) of 0.02 nanoamps per micron, is well suited for power-sensitive circuits in a chip. For speed critical chips, the HP transistor provides a typical ring oscillator (RO) delay of 7.4 picoseconds per stage. The design manual will be updated in fourth quarter of 2003 to include HP devices. The SPICE simulation models currently available to Chartered 90nm customers and IP partners were developed using a methodology that isolates and partitions numerous process variables. This streamlines both initial development cycles on 200-mm wafers and migration to 300-mm.

To: Cary Salsberg who wrote (7211)	9/18/2003 1:24:33 PM
From: Proud_Infidel	Respond to of 25522

Applied Materials says industry M&A could be slow Thursday September 18, 1:13 pm ET SAN FRANCISCO, Sept 18 (Reuters) - High stock prices will hinder merger and acquisition activity in the $20 billion semiconductor equipment industry as it recovers from its worst slump ever, the chief financial officer of chip equipment company Applied Materials Inc.(NasdaqNM:AMAT - News) said on Thursday. Still, Joseph Bronson said Applied Materials will look to build its consumable products business through acquisitions as well as internal growth, "I think there'll probably not be a lot of consolidation as we get into an upturn because of valuation," Bronson told investors at a Banc of America Securities (News - Websites) conference. "In the equipment space a lot of things could have happened but didn't happen," he added, because of executive personalities and "ego," as well as stock valuation. Investors have been betting for more than half a year on a chip industry recovery. The Philadelphia Stock Exchange semiconductor index (Philadelphia:^SOXX - News) has gained almost 80 percent since February. Shares in Applied Materials have moved almost in lock-step with that rally, gaining just over 80 percent since early March, boosting the company's value to $34.5 billion. Santa Clara, California-based Applied Material, the largest provider of the equipment used to build circuits on discs of silicon, has honed in on growing its consumable products business, Bronson said. Products such as pads and slurries are regularly reordered by chip producers, providing a steadier stream of revenue. "We have a major focus on making that business bigger," Bronson said. In response to a question, he said the company expected to grow the business both through acquisitions and through internal development. Sales of equipment used to build, test and package microchips has suffered in the past three years following a period of over-investment in the late 1990s by chip makers. Bronson said the company's spare parts business has picked up, which could suggest that chip factories are busier and operating closer to their capacity limits.

To: Cary Salsberg who wrote (7211)	9/19/2003 9:27:21 AM
From: Proud_Infidel	Respond to of 25522

CNT has ten times transconductance of MOS, NEC eyes 2010 intro By Peter Clarke Silicon Strategies 09/19/2003, 8:21 AM ET TOKYO -- NEC Corp. said Friday (September 19, 2003) that engineers working for the company have developed a "stable" fabrication technology for carbon nanotube transistors (CNTs). NEC added that CNTs produced using the fabrication technology attain more than ten times greater transconductance than silicon MOS transistors. NEC said it would continue to work on CNT control technology, electric characteristic control, device structure design, and fabrication process development with the aim of realizing a CNT suitable for commercial deployment by 2010. Transconductance measures the change in drain current in response to a change in input gate voltage. The larger this value the greater the operation speed of the transistor, NEC said. One key step in the research was the development of a chemical vapor deposition (CVD) method that uses a catalyst to promote CNT growth on a silicon substrate, said NEC. This technology enables control of the CNT position on the silicon substrate, something other techniques have found difficult. A second development is a process for the formation of electrodes with low contact resistance between the electrodes and the carbon nanotube. It should be possible to achieve as much as 20 times greater transconductance as compared with silicon MOS transistors by removing parasitic resistance between source and drain electrodes, NEC said.