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To: Dan3 who wrote (103511)	10/22/2003 1:58:49 PM
From: ptanner	Read Replies (1) \| Respond to of 275872

re: "My understanding is that DMA devices access the memory through HT links" Yes, there wouldn't need to be a specific # of address lines as it would be over HT link from the chipset to the CPU. However, there must be some reason there is a limit within the chipset or why would Via note a 4GB limit for the K8T800? And 4GB isn't really a limit given presently available memory for desktop systems but we one always wishes for future expansion. The lowest PW listing for 2GB has dropped from $1000+ to only $600 since I last checked. But this does mean that the non-AMD K8 chipsets will have limited application for the high-end enthusiast/workstation folks who want to play with >4GB RAM for their 64-bit Linux OS system. -PT

To: Dan3 who wrote (103511)	10/22/2003 2:04:59 PM
From: combjelly	Respond to of 275872

" No work need be done by the "local" CPU "core"" Exactly. The memory controller, CPU (actually the L1 cache) and HTT links are connected to a crossbar switch that can connect any two together on demand. So something on one of the HTT busses can access memory with no intervention from the CPU. THis is also how the CPU can access memory on another CPU, with the addition of the accesses being snooped by the other CPUs. I am guessing that every transaction is snooped, this way if data hasn't been written through the cache the proper information can be supplied (and probably written to memory at that time) and if the memory is modified, then those cache entries can be invalidated.