Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Pravin Kamdar who wrote (103688)	10/26/2003 2:11:18 PM
From: dougSF30	Respond to of 275872

Pravin & Pete, Yeah the guys at iHub have similar objections to your (Pete's) theory. Plus they point out that SRAM is the first thing the process is qualified for, so "leaky L2 cache" isn't likely either. Doug

To: Pravin Kamdar who wrote (103688)	10/26/2003 8:28:33 PM
From: pgerassi	Read Replies (2) \| Respond to of 275872

Dear Pravin: How many points are used in the coverage ranges? 2, 3, 5, 10 or more holding all other parameters stable? Did they check all transistor combinations or some more limited set? And if you do not see a minor leakage mode in 130nm, do they test for it in 90nm? Or do they assume it will fit in the curve best fit from 1um down to 130nm and extend the results to 90nm? Did they use the same successful model at 130nm and plugged in the numbers for 90nm? The last misses knee type situations where the discontinuity is just lower than the last generation. That is why the real world emperical results trump all of the modeled ones. And why silicon dies are the "acid" test of a design. Pete