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To: StanX Long who wrote (13594)	2/25/2004 10:24:12 PM
From: StanX Long	Read Replies (1) \| Respond to of 95391

Applied, Cadence, Canon take 'X' to 65-nm, claims group By Peter Clarke Silicon Strategies 02/25/2004, 10:16 AM ET SAN JOSE, Calif. -- Chip making equipment supplier Applied Materials Inc., working with EDA firm Cadence Design Systems Inc., and lithography equipment supplier Canon Inc. has produced a chip that uses 'diagonal' metalization and 65-nanometer manufacturing process technology, the X Initiative said Wednesday (February 25, 2004). The X Initiative is a semiconductor supply-chain consortium that promotes the use of diagonal 45 degree routing as well as conventional north-south, east-west Manhattan style routing of interconnect on integated circuits. The design style can result in fewer vias, reduced die area and improved performance the X Initiative claims. The latest announcement was made at the SPIE lithography conference, being held in Santa Clara, California. The work was done at Applied's Maydan Technology Center in Sunnyvale, California and the interconnect test chip demonstrates the manufacturability of the X Architecture designs for advanced copper/low-k chips using existing process technologies, the X Initiative said. It was announced that Applied had manufactured a 90-nm test chip in June 2003. Cadence provided the test structure design and chip validation tools for the project while Canon's ArF (197-nm wavelength) imaging system was employed for the wafer lithography, the group said. Applied Materials used its interconnect fabrication technologies to produce the multi-layer copper/low-k interconnect on 300-mm wafers, the X Initiative said. "Our work with Cadence and Canon on this 65-nm intermediate layer interconnect test chip provides further confirmation of the manufacturing readiness and scalability of X Architecture designs for future process nodes," said John Lee, general manager of Applied Materials' Maydan Technology Center, in a statement. However, details were not given of the half-pitch of the interconnect and an "intermediate layer" interconnect would not normally be of relaxed critical dimensions compared with lower levels of metallization closer to the silicon surface. "Applied Materials, along with Canon and Cadence, are once again leading the industry by proving the manufacturability of the X Architecture at the 65-nm process node, ahead of end-user production lines," said Aki Fujimura, X Initiative steering group member and chief technology officer of new business incubation at Cadence, in the statement issued by the X Initiative. Two papers are due to be presented at SPIE on Thursday, February 26 from 10:20 a.m.-12:20 p.m., that provide more details on the fabrication of the 90-nm and the 65-nm test chips, the X Initiative dsaid. The papers are titled: "Manufacturability of the X Architecture at the 90-nm technology node" and "Taking the X Architecture to the 65-nanometer technology node"